KR100369332B1 - High integration semiconductor device - Google Patents
High integration semiconductor device Download PDFInfo
- Publication number
- KR100369332B1 KR100369332B1 KR1019940016517A KR19940016517A KR100369332B1 KR 100369332 B1 KR100369332 B1 KR 100369332B1 KR 1019940016517 A KR1019940016517 A KR 1019940016517A KR 19940016517 A KR19940016517 A KR 19940016517A KR 100369332 B1 KR100369332 B1 KR 100369332B1
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- KR
- South Korea
- Prior art keywords
- gate electrode
- implanted
- tungsten silicide
- transistor
- film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 230000010354 integration Effects 0.000 title abstract 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 230000002093 peripheral effect Effects 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000006731 degradation reaction Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Abstract
Description
본 발명은 반도체 소자 제조 분야에 관한 것으로 특히, 텅스텐 실리사이드 형성으로 인한 셀 영역 게이트 산화막의 열화를 방지할 수 있는 고집적 반도체 소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a highly integrated semiconductor device capable of preventing deterioration of a cell region gate oxide film due to tungsten silicide formation.
종래, 셀 영역과 주변회로 영역에 위치하는 NMOS 트랜지스터 각각의 게이트 전극은 n+이온주입된 폴리실리콘막과 n+이온이 주입된 텅스텐 실리사이드막의 적층 구조로 이루어진다.Conventionally, the gate electrode of each of the NMOS transistors located in the cell region and the peripheral circuit region has a stacked structure of an n + ion implanted polysilicon film and an n + ion implanted tungsten silicide film.
상기와 같은 구조의 게이트 전극을 이루는 텅스텐 실리사이드막을 형성하기 위해서는 WF6가스가 사용된다. WF6의 불소는 게이트 산화막을 열화시키며, 게이트 전극 상부에 형성되는 텅스텐 실리사이드막은 게이트 산화막에 스트레스를 주게 된다. 따라서, 반도체 소자의 수율 감소 및 소자의 신뢰성 저하 문제가 발생되는데, 특히 트랜지스터가 많이 형성되는 셀 영역에서는 오동작하는 트랜지스터가 형성될 확률이 상대적으로 높다.WF 6 gas is used to form the tungsten silicide film forming the gate electrode of the above structure. The fluorine of WF 6 degrades the gate oxide film, and the tungsten silicide film formed on the gate electrode stresses the gate oxide film. Therefore, there is a problem of decreasing the yield of the semiconductor device and deterioration of the reliability of the device. In particular, in a cell region in which many transistors are formed, there is a relatively high probability of forming a malfunctioning transistor.
따라서, 상기 문제점을 해결하기 위하여 안출된 본 발명은 셀 영역과 주변회로 영역의 게이트 전극의 구조를 달리하여 즉, 셀 영역의 게이트 전극은 폴리실리콘막 상부에 텅스텐 실리사이드막을 형성하지 않아 게이트 산화막의 열화를 방지하고, 게이트 산화막의 스트레스를 줄여 반도체 소자의 수율 증가 및 제조비용을 절감시킬 수 있는 고집적 반도체 소자를 제공하는데 그 목적이 있다.Therefore, the present invention devised to solve the above problems is different in the structure of the gate electrode of the cell region and the peripheral circuit region, that is, the gate electrode of the cell region does not form a tungsten silicide film on the polysilicon film deterioration of the gate oxide film The purpose of the present invention is to provide a highly integrated semiconductor device capable of reducing the stress of the gate oxide layer and reducing the yield and manufacturing cost of the semiconductor device.
상기 목적을 달성하기 위한 본 발명은, 불순물이 이온주입된 폴리실리콘막으로 이루어지는 게이트 전극을 갖는 제1 트랜지스터를 구비하는 셀 영역; 및 불순물이 이온주입된 폴리실리콘막과 불순물이 이온주입된 텅스텐 실리사이드막의 적층 구조로 이루어지는 게이트 전극을 갖는 제2 트랜지스터를 구비하는 주변회로 영역을 포함하는 반도체 소자를 제공한다.The present invention for achieving the above object is a cell region comprising a first transistor having a gate electrode made of a polysilicon film implanted with impurities ion; And a peripheral circuit region including a second transistor having a gate electrode formed of a stacked structure of a polysilicon film implanted with impurities and a tungsten silicide film implanted with impurities.
이하, 첨부된 도면 제 1 도 내지 제 3 도를 참조하여 본 발명에 따른 고집적 반도체 소자의 게이트 전극 구조를 상세히 설명한다. 도면에서 도면부호 '1'은 기판, '2'는 소오스/드레인, '3'은 게이트 산화막, '4'는 폴리실리콘막, '5'는 스페이서 산화막, '6' 및 '7'은 텅스텐 실리사이드막을 각각 나타낸다.Hereinafter, a gate electrode structure of a highly integrated semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 to 3. In the drawings, reference numeral '1' is a substrate, '2' is a source / drain, '3' is a gate oxide film, '4' is a polysilicon film, '5' is a spacer oxide film, and '6' and '7' are tungsten silicide Each film is shown.
본 발명에 따른 고집적 반도체 소자는 n+불순물이 이온주입된 폴리실리콘막으로 이루어지는 게이트전극을 갖는 트랜지스터를 셀 영역에 구비한다. 그리고, 주변회로 영역에는 n+불순물이 이온주입된 폴리실리콘막 및 n+불순물이 이온주입된 텅스텐 실리사이드막으로 이루어지는 적층구조의 게이트 전극을 갖는 NMOS 트랜지스터와, p+불순물이 이온주입된 폴리실리콘막 및 p+불순물이 이온주입된 텅스텐 실리사이드막의 적층구조의 게이트 전극을 갖는 PMOS 트랜지스터를 구비한다.The highly integrated semiconductor device according to the present invention includes a transistor having a gate electrode made of a polysilicon film implanted with n + impurities in a cell region. The peripheral circuit region includes n + impurity ions, and the implanted polysilicon layer and the n + impurity NMOS transistor having a gate electrode of a laminate structure made of an ion-implanted tungsten silicide film, p + impurity is ion-implanted polycrystalline silicon film And a PMOS transistor having a gate electrode having a stacked structure of a tungsten silicide film implanted with p + impurities.
제 1 도는 셀 영역에 위치하는 본 발명에 따른 트랜지스터의 게이트 구조를 보이는 단면도로서, 텅스텐 실리사이드를 형성하지 않고 이온주입된 폴리실리콘막(4)으로만 이루어지는 게이트 전극을 보이고 있다.FIG. 1 is a cross-sectional view showing a gate structure of a transistor according to the present invention located in a cell region, showing a gate electrode made of only a polysilicon film 4 implanted with ion without forming tungsten silicide.
그리고, 주변회로 영역에 형성되는 NMOS 트랜지스터는 제 2 도에 도시된 바와 같이 폴리실리콘막(4) 및 As 등과 같은 n+불순물이 이온주입된 텅스텐 실리사이드막(6)의 적층구조로 이루어지는 게이트 전극을 갖는다.As shown in FIG. 2, the NMOS transistor formed in the peripheral circuit region includes a gate electrode having a stacked structure of a polysilicon film 4 and a tungsten silicide film 6 into which n + impurities such as As are ion-implanted. Have
또한, 주변회로 영역의 PMOS 트랜지스터는 제 3 도에 도시된 바와 같이 폴리실리콘막(4) 및 B 등과 같은 p+불순물이 이온주입된 텅스텐 실리사이드막(7)의 적층구조로 이루어지는 게이트 전극을 갖는다.In addition, the PMOS transistor in the peripheral circuit region has a gate electrode formed of a stacked structure of a polysilicon film 4 and a tungsten silicide film 7 implanted with p + impurities such as B and the like.
여기서, 상술한 n+또는 p+불순물이 이온주입된 텅스텐실리사이드막(7)은 텅스텐실리사이드막(7)에 n+또는 p+불순물을 이온주입하여 형성된다.Here, the aforementioned n + or p + impurity is ion-implanted tungsten silicide film 7 is formed by ion implantation of n + or p + impurities in the tungsten silicide film (7).
상기와 같이 이루어지는 본 발명은 셀 영역에 형성되는 게이트 전극의 상부에 텅스텐 실리사이드막을 구비하지 않음으로써 셀영역 게이트 산화막의 열화 방지 및 스트레스를 줄여 반도체 소자의 수율 증가 및 제조비용의 절감을 이룰 수 있어 특히 고집적화되는 256M DRAM 및 1G DRAM 이상의 소자 제조를 용이하게 할 수 있는 효과가 있다.According to the present invention, the tungsten silicide film is not provided on the gate electrode formed in the cell region, thereby preventing degradation of the cell region gate oxide film and reducing stress, thereby increasing the yield of semiconductor devices and reducing the manufacturing cost. There is an effect of facilitating the fabrication of more than 256M DRAM and 1G DRAM that are highly integrated.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. Will be evident to those who have knowledge of
제 1 도는 본 발명에 따른 셀 영역 NMOS 트랜지스터의 단면도,1 is a cross-sectional view of a cell region NMOS transistor according to the present invention,
제 2 도는 본 발명에 따른 주변회로 영역 NMOS 트랜지스터의 단면도,2 is a cross-sectional view of a peripheral circuit region NMOS transistor according to the present invention;
제 3 도는 본 발명에 따른 주변회로 영역 PMOS 트랜지스터의 단면도.3 is a cross-sectional view of a peripheral circuit region PMOS transistor according to the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1: 기판 2: 소오스/드레인1: substrate 2: source / drain
3: 게이트 산화막 4: 폴리실리콘막3: gate oxide film 4: polysilicon film
5: 스페이서 산화막 6,7: 텅스텐 실리사이드막5: spacer oxide film 6,7: tungsten silicide film
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940016517A KR100369332B1 (en) | 1994-07-08 | 1994-07-08 | High integration semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940016517A KR100369332B1 (en) | 1994-07-08 | 1994-07-08 | High integration semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960005893A KR960005893A (en) | 1996-02-23 |
| KR100369332B1 true KR100369332B1 (en) | 2003-03-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940016517A KR100369332B1 (en) | 1994-07-08 | 1994-07-08 | High integration semiconductor device |
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| Country | Link |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61101075A (en) * | 1984-10-24 | 1986-05-19 | Hitachi Ltd | Manufacture of semiconductor device |
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- 1994-07-08 KR KR1019940016517A patent/KR100369332B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61101075A (en) * | 1984-10-24 | 1986-05-19 | Hitachi Ltd | Manufacture of semiconductor device |
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| KR960005893A (en) | 1996-02-23 |
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