DE3446928A1 - SEMICONDUCTOR ARRANGEMENT - Google Patents

Description

The invention relates to a semiconductor arrangement as specified in the preamble of claim 1, as well as a Process for their manufacture. It relates in particular to a semiconductor device with an electrostatic Protective layer and an internal circuit, which is provided on the same semiconductor substrate with e.g. an MIS (Metal-insulator-semiconductor) element used as an internal circuit is formed.

The miniaturization of semiconductor devices (IC) has been undertaken in order to increase their operating speed and to improve their integration density. MOS elements (MOSFETs), the typical examples of MIS elements (MISFETs) are no exception. To MOS elements to downsize, their gate oxide films are reduced in thickness and the length of their canals has become shorter and shorter. That means a relatively strong electrical Field is generated in the arrangement, so that an injection of hot charge carriers into the gate oxide film occurs, and the threshold voltage shifts or there is a deterioration (degradation) in the slope.

A double diffused drain structure as shown in Fig. 1 has been proposed to solve these problems. Fig. 1 shows a section through a typical N-channel MOSFET. Reference numeral 1 denotes a P-doped silicon semiconductor substrate, 2 a silicon dioxide (SiO ₂ ) film, 3 a gate oxide film, and 4 a gate electrode. In order to reduce the strong electric field in the vicinity of the drain region, both the drain and the source have a double-diffused drain structure, which consists of an N-like layer 5 with phosphorus (P) and an N -like layer 6 with arsenic (As) doping exists (see E. Takeda et al. "An As-P (N + -) Double Diffused Drain MOSFET for VLSI's", Digest of Technical Papers, Symp. On VLSI Technology, 0ISO, Japan, pages 40-41 ( Sept. 1982), to which reference is hereby made

is taken)

A protection circuit is usually built on the same semiconductor substrate formed to prevent the MIS element constituting the circuit from abnormal signals from outside the IC-derived signals, to protect. According to Fig. 12, the protection circuit (i.e., the electrostatic protection circuit) is a circuit for preventing the destruction of the gate insulating film of a MISFET 71 of a first-stage inverter 68 whose gate electrode is connected to the "pad 8 via fine resistor 10 is connected. A destruction occurs when electrostatic energy is applied to the pad.

A circuit such as that shown by the equivalent circuit diagram of Fig. 2 is a typical protection circuit 9, which is used to protect circuits other than the protection circuit, i.e. the internal one Circuit IC »A signal for the internal circuit is connected to a connection pad 8 via a diffused resistor 10 created, one end of which with the connection spot 8 is connected, a clamping MOSFET 11, the gate of which and source are grounded, connected to the interface between the resistor 10 and the internal circuit.

The inventors of the present invention have examples of semiconductor devices having the double diffused drain structure and found the following problem.

In this semiconductor device, the protection circuit also has a double-diffused drain structure. A section through this circuit 9 is shown in FIG. In this figure, reference numeral 12 designates a P-type silicon semiconductor substrate, with 13 a SiO ₂ ~ insulation film is designated, with 10 a resistor, with 11 a clamping MOSFET,

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with 14 a source region, with 15 a gate oxide film, with 16 a gate electrode, with 17 a phosphosilicate glass film (PSG), and with 18 an aluminum electrode. Both the diffused Resistor 10 and the semiconductor regions of the source and drain regions of the clamping MOSFET 11 have the double diffused drain structure and consist of an N -like layer and an N -like layer.

In a semiconductor device of this type, however, an insulation film of a MISFET that j

forms a first-stage inverter and which has a double diffuse dated drain area has. That is, because the reverse breakdown voltage at the boundary layer (diode) of the MISFET, which has a double diffused drain, increases, the electrostatic energy is exerted on the insulating film before it reaches the substrate due to breakdown of the clamping MIS-FET can drain.

It is therefore the object of the present invention to provide a half { specify ladder arrangement in which both the deterioration | tion of the properties that arise from hot charge carriers stirs how the deterioration of the destructive voltage diminishes and also to provide a method for manufacturing such a semiconductor device.

Another aim of the invention is to specify semiconductor devices, in which an internal circuit is protected by an electrostatic protection circuit, and methods for To provide manufacturing of such semiconductor devices.

This task "is carried out with a semiconductor device according to the The preamble of claim 1 solved, according to the invention the specified in the characterizing part of this claim Has features.

Further, advantageous refinements of the invention and methods for producing the semiconductor arrangement according to the invention are specified in the subclaims.

In the semiconductor device according to the invention, there is internal circuit made of a double diffused drain structure, to reduce the deterioration in properties resulting from hot charge carriers, where the protection circuit comprises a simply diffused drain structure so that the intensity of the field acting on the gate oxide film the e.g. clamping MOSFET acts, can be reduced, so that a semiconductor device having a high withstand voltage can be obtained.

In the following, the invention is described and explained in more detail with reference to the exemplary embodiments shown in the figures. Show it

1 shows a cross section through an N-channel MIS element with

> a double diffused drain structure; 2 shows an electrical equivalent circuit diagram for an example of an electrostatic protection circuit; Fig. 3 shows a section through a special device,

which corresponds to the equivalent circuit diagram of FIG. 2; Fig. 4 is a plan view showing an example of the chip pattern a DRAM provided with an electrostatic protection circuit and an internal protection circuit built on the same semiconductor substrate;

Fig. 5

8 to 8 sections through the semiconductor device to illustrate the manufacturing method according to an embodiment the invention; Fig. 9

and FIG. 10 is schematic plan views showing the electrostatic protection circuit and the internal circuit, respectively, of FIG Fig. 8 correspond;

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11 shows the experimental results in a diagram for the dielectric breakdown voltage of an electrostatic protection circuit with a simple diffused drain structure compared with the electrostatic protection circuit with a double

diffused drain structure;

12 shows a circuit diagram of an electrostatic protection circuit and a special internal circuit protected by it; and

Fig. 13

and 14 each show the application of the present invention in circuit diagrams Invention to a MISFET, which forms the first stage of an input buffer, and to one MISFET, which forms the last stage of an output buffer.

In the following, an embodiment of the semiconductor device and the method for producing it according to FIG Invention explained with reference to FIGS. 4 to 10. However, these explanations are not a limitation of the Invention. '

FIG. 4 shows an example of a layout of a chip 7 for a DRAM according to an exemplary embodiment of the invention. Reference numeral 8 denotes a connection pad, and 9 denotes a protective circuit which is used for each connection pad is provided, with 100 a signal generator circuit is designated, which generates read and write clock signals, etc., 101 denotes a memory field in which MIS elements as Memory cells are used, and 102 denotes column and row decoders. These parts form the DRAM chip (dynamic memory with random access).

5 to 8 show, step by step, in cross sections, the manufacturing method for a semiconductor device according to an example of the invention. The protection circuit is on

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the left side of each figure, and is a memory cell which is part of the internal circuit shown on the right. FIG. 8 is a section through a complete semiconductor device, and FIG. 9 and 10 are schematic plan views of the semiconductor device of FIG. 8.

Fig. 5 is a cross-sectional view showing the state of the manufacturing process which has progressed to the formation of the gate electrode of the MOSFET of the DRAM using a conventional technique. In the drawing, reference numeral 20 denotes a semiconductor substrate, 21 a gate oxide film, and 22 a gate electrode. The semiconductor substrate 20 is, for example, a P-doped monocrystalline silicon substrate with a (100) crystal plane, and the gate oxide film 21 is, for example, an SiO ₂ film. The gate electrode 22 is a conductive layer which forms a second layer, and it is produced by depositing polycrystalline silicon using a CVD method and then diffusing phosphorus ions, inter alia, to form polycrystalline silicon with reduced resistance. The gate electrode can consist of a metal layer with a high melting point, a layer of a suicide of such a metal, or a double-layer structure consisting of polycrystalline silicon and the silicide of a metal with a high melting point. The circuit shown in Fig. 2 is shown as an example of a protection circuit on the left side of Fig. 5, and the memory cell of the DRAM is shown as an example of the internal circuit on the right side of the figure.

Reference numeral 23 denotes a thick oxide film for insulation, which is formed by selective thermal oxidation of the surface of the silicon substrate 20, for example. _{A silicon nitride film (Si 3} N ₄ ) 25 serving as a dielectric film of a storage capacitor is on the upper

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Surface of the field oxide film 23 formed on the memory cell side, and also on the surface of a thin SiO ₂ film 24, which extends from the film 23, via the thin film 25, an electrode 27 made of polycrystalline silicon is deposited on a SiO2 film 26, which is diffused with phosphorus ions, among other things, in order to reduce its resistance. The conductive layer, which is the first layer consisting of this polycrystalline silicon electrode, forms one of the electrodes of the capacitor of the memory cell. Incidentally, at this stage, ion implantation for an inversion preventing layer (ie, a channel stopper layer) or for controlling the threshold voltage, etc. is already carried out.

According to FIG. 6, on the surface of the protective circuit alone, a photoresist film 28 is selectively formed by a photolithographic process. In particular is the photoresist film 28 (1 μΐη) only over the area A of the Fig. 4 formed. Then using this Fo-. toresistfilmes 28 designed as a mask ion implantation. leads to the N ~ -doped layer of the double diffused drain structure over the entire surface of the semiconductor arrangement to create. In this ion implantation, e.g. phosphorus ions are used as N-dopants, and with After the implantation, an N -type diffusion layer 29 is formed formed as a source-drain region. The dose is 1 · 10 / cm, the implantation energy 50 keV arsenic ions can be used as a dopant.

Referring to Fig. 7, the photoresist film 28 is removed, and then arsenic ions are implanted to form an N -type Layer 30 of the double diffused drain structure and a diffusion resistance layer 31 of the protective circuit such as also the source-drain region 32 of the clamping MOSFKT to biidt-n.

1S 2
The dose is 8 10 / cm, the implantation energy 80 keV. Phosphorus ions can be used as dopants.

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As can be seen from this, the diffusion resistance formed from a polysilicon layer, i.e. formed on the entire semiconductor substrate.

As can be seen from FIGS. 6 and 7, the protection circuit has a single diffused drain structure, while the internal circuit has the double diffused drain structure owns. In this case, the photoresist film 28 is selectively formed to prevent the implantation of the N -type phosphorus ions to prevent in the protection circuit. The implantation of phosphorus ions in the protective circuit can also can be prevented by controlling the scanning (scanning) of the ion implantation (to scan the protective circuit enclosing area, i.e. area A in Fig. 4), because it is because the electrostatic Protection circuit usually in the always existing arrangement in a certain area around the periphery of the Chip according to FIG. 4 is formed, relatively easy to suppress the ion implantation scan by is so limited that it leaves out this area.

After the electrostatic protection circuit with the simply diffused drain structure and the internal circuit with of the double diffused drain structure are formed in this way, as shown in FIG. 8, a phosphosilicate glass film becomes (PSG-FiIm) 33 and an aluminum layer serving as a third conductive layer. The aluminum layer serves as an output electrode 34 for the diffusion resistor 31, as an output electrode 35 of the internal Circuit, as source electrode 36, and as data line 37 of the memory cell. By the way, after training the PSG film 33 used photoetching to form the contact holes for these electrodes and to form the Electrodes are sputtered on aluminum. Finally will a PSG film 38 is formed as a protective film.

9 and 10 show schematic plan views of the electrostatic protection circuit and the internal circuit, respectively of Fig. 8. The section along the line B-B of Fig. 9 corresponds to the protective circuit area, the section along the line C-C of FIG. 10 to the area of the internal circuit of FIG. 8.

In Fig. 9, reference numeral 40 denotes a connection pad, 41 a Dxffusxonsschicht for an input part, 42 a contact hole and 43 a diffused resistor was standing. The reference number 44 denotes a clamping MOSFET, which consists of a region 45 electrically connected to the diffused resistor 43 a gate electrode 46 and a source region 47. The region 45 is connected to an Al signal line 45B via contacts 45A and the Al signal line 45B is electrically connected to the internal circuit. In a similar way the source region 47 is connected to an Al line 47B via contacts 47A, and the Al line 47B is connected to it one end connected via a contact 48 to the gate electrode and the other end to ground.

In Fig. 10, reference numeral 50 denotes a boundary line of the field oxide film, which is the active area of the memory cell and the reference numeral 51 denotes a word line made of polycrystalline silicon which the Gate electrode of the MOSFET corresponds. Reference numeral 52 denotes polycrystalline silicon which is one of the Electrodes of the capacitor of the memory cell are used, and 53 denotes an aluminum electrode with a contact hole 54 of the data line is wired.

11 shows the typical experimental ones in a diagram Results for comparing the electrostatic destruction voltage of a protective circuit with a simple one "diffused drain structure with that of a protection circuit

with double diffused drain structure.

The percentage failure rate ratio is along the Plotted on the ordinate, the electrostatic destruction voltage (V) along the abscissa. The segment-like line (a) denotes the results of the double diffused drain structure, the segment-like line (b) that of the simply diffused drain structure. The dielectric strength of the same Terminal pins of five samples were examined. The diagram shows that a protective circuit with a simply diffused drain structure a much better one Has electrostatic destruction voltage.

Because, as described above, the protection circuit has a single diffused drain structure and the internal circuit has a have double diffused drain structure, can reduce the electric field concentration in the internal circuit and doping the electric field concentration in the gate oxide film of the first-stage MISFET of the internal circuit which counteracts both hot charge carriers and a destruction voltage.

Since the protective circuit has a mask to prevent the formation of one of the diffusion layers of the double diffused When the drain region is used, the semiconductor device of the present invention can be easily manufactured by adding just a single photolithographic step.

When a method of local control of ion implantation scanning is used to exclude the protection circuit that is in a permanent arrangement or is local, the present invention can be carried out with a simple manufacturing process.

Although the invention with reference to special features

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Management examples has been described, it is not limited to them, but can be modified in various ways. For example, in one embodiment, the protection circuit consists of a diffused resistor and a clamp MOSFET, but it is on top of it

not restricted and can be applied to various other protective circuits that at least break the boundary layer in a diffusion layer and the surface breakthrough at the drain end of a clamp MOSFET to improve dielectric breakdown voltage.

Furthermore, the clamp MOSFET by one or two boundary ^;

layer diodes are replaced. In this case, the border \ is layer of the diode between an N -type layer simultaneously with the N -type layer 30 is formed 31 and 32, and formed the P-type substrate. Furthermore is a. DRAM has been described as an example of the internal circuit, but the internal circuit is not limited to a DRAM, but can include any circuit provided with MIS elements which has at least one double-diffused drain structure. Thus, the present invention can be applied to a MISFET having a single diffused drain structure, a MISFET which is the first stage of an input buffer, and a MIS-FET which is the last stage of an output buffer. With regard to the circuit diagrams for such MISFETs with a single diffused structure, which are used in the MISFET forming the first stage of an input buffer and the MISFET forming the last j stage of an output buffer, reference is made to FIGS. 13 and 14. In these Fig.

13 and 14, reference numerals 81 and 82 denote an input pad and an output pad, and the structure surrounded by dashed lines 83,84 represents the simply diffused drain structure. j

Furthermore, the invention can be applied to N-channel MISFETs of a CMISIC]

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- ι ο -

(integrated circuit with complementary MIS elements), in the case of N-channel MOSFETs in a P-well region or a P substrate are formed, can be applied.

Figs. 15, 16 and 17 show circuit diagrams for such CMISIC. The structure surrounded by the dashed lines 85, 86 and 87 represents the one that was simply diffused Drain Structure- The structures of MISFETs 88, 89 and 90 of FIG. 15 are shown in FIG. The N-Channel MIS-FET 89 has a double diffused drain structure with an N-like layer 58 and an N -like layer 59 formed in a P-type substrate 5 6. P -like regions 61 serve as source and drain regions of the P-channel MISFET 90/3 in an N -like well area 57 is formed. In the substrate 56 is the MISFET 88 with a simply diffused drain structure with the N-like Layer 60 is formed. A diode 91 has the same structure as the MISFET 88. Area diodes (Junction diodes) 93, 94, 96 and 97 are between the P-substrate and an N -doped layer such as the N-type Layer 60, formed, which is formed at the same time with the individual drain regions of the MISFETs. By doing Case where a resistor 92 is made from an N -doped layer such as layer 60 the diode 94 can be practically formed between the resistor 92 and the P-substrate 56.

The present invention can further be applied to a case where N-channel MISFETs 91 are the ones shown in FIG. 19 Have the structure shown. The source and / or the drain region of the MISFET 91 comprises an N ~ -like layer 64 formed in self-alignment with a gate electrode 65 and an N -type layer 63 formed in self-alignment is formed with a sidewall spacer 62 and the gate electrode 65. The MISFET 91 replaced for example the MISFET 89.

Although the above description has focused on a DRAM and its protection circuit, so can the The invention also applies to ordinary integrated circuits with a MOS structure such as DRAMs (e.g. DRAMs with 256 K bits), SRAMs, MOS logic circuits, etc. are used.

RS / bi

Claims (16)

PATENTANWÄLTE STREHL SCHÜBEL-HOPF SCHULZ 34 469 28 WIDENMAYERSTKASSE 17, D-8000 MUNICH 22 HITACHI, LTD. DEA-26943 December 21, 1984 Semiconductor device ■ Ν 1. } Semiconductor arrangement with a first circuit, which is provided with at least one MIS element, and with a second circuit, which is electrically connected to the first circuit, characterized in that the first circuit (IN) and the second circuit (9) are formed on the same semiconductor substrate (12, 20), that the first circuit has a double diffused drain structure and the second circuit (9) a single diffused Has drain structure. 2. Semiconductor arrangement according to claim 1, characterized in that "indicates, that the first circuit is an internal circuit (IN), that the second circuit (9) is an electrostatic protection circuit is, and that the electrostatic protection circuit for Protection of the internal circuit from abnormal external signals is provided. 3. Semiconductor arrangement according to claim 1 or 2, characterized in that that the electrostatic protection circuit (9) at least one diffused resistor (10, 31) and at least a clamping MIS element (11, 44). 4. Semiconductor arrangement according to one of claims 1 to 3, characterized in that that the diffused resistor (10, 31) has a simply diffused drain structure. 5. Semiconductor arrangement according to one of claims 1 to 4, characterized in that an input pad (8, 40) is provided, and that the resistor (11, 31) is electrically connected to the internal Circuit (IN) and the connection pad (8, 10) is connected. 6. Semiconductor arrangement according to one of claims 1 to 5, characterized in that that an output pad is provided, and that the electrostatic protection circuit (9) electrically with connected to the output pad. COPY 7. Semiconductor arrangement according to one of claims 1 to 6, characterized in that that the internal circuit (IN) has a dynamic RAM element. 8. Semiconductor arrangement according to one of claims 1 to 7, characterized in that a first diffusion layer (29) for forming the MIS element, a second diffusion layer (30) for the MIS element and a diffusion layer (31) for the second Circuit (9) are provided, the first diffusion layer (29) and the second diffusion layer (30) a Form double diffused drain structure. 9. A method for producing a semiconductor arrangement according to one of claims 1 to 8 with a first circuit (IN), which has at least one MIS element, and with a two-tone circuit (9), which is electrically connected to the first circuit is connected, the first and second circuits formed on the same semiconductor substrate are, marked by the following process steps: Forming a mask (28) over the area of the second circuit (9) and then forming a first Diffusion layer (29) for the MIS element, COPY Removing the mask and forming a second diffusion layer (30) for the MIS element and a diffusion layer (31) for the second circuit (9) such that the first circuit a double diffused drain structure and the second circuit a single diffused drain structure obtain. 10. A method for producing a semiconductor device according to claim 9, characterized in that a photoresist film is used to manufacture the mask will. 11. A method for manufacturing a semiconductor device according to claim 9 or 10, characterized in that for the production of the first and second diffusion layers (29, 30) and the diffusion layer (31) for the second circuit (9) an ion implantation is carried out. 12. The method for producing a semiconductor arrangement according to one of claims 9 to 11, characterized in that for the production of a first N ~ diffusion layer (29) an ion implantation with phosphorus ions and for the production "" j ■■ development of an N -like second diffusion layer (30) and an N -like diffusion layer (31) for the electrostatic protective layer, an ion implantation with arsenic ions is performed. 13. A method for producing a semiconductor arrangement according to any one of claims 9 to 12,
characterized in that the second diffusion layer (30) and the diffusion layer (31) of the second circuit (9) are formed simultaneously. 14. A method for manufacturing a semiconductor device with a first circuit provided with an MIS element (IN) and a second circuit (9) electrically connected to the first circuit, the first and the second Circuit are formed on the same semiconductor substrate, characterized by the following process steps: Performing an ion implantation scan only through the Area of the first circuit (IN) of the semiconductor arrangement for forming a first diffusion layer (29) for the MIS element, Perform a second ion implant scan via the entire surface of the semiconductor arrangement to form a second diffusion layer (30) for the MIS element and a diffusion layer (31) for the second circuit 9 such that the first circuit (IN) has a double drain structure and COPY the second circuit received a Kinfach-Drain-iH.rukt.ur. 15. A method for producing a semiconductor arrangement according to one of claims 9 to 14, characterized in that the electrostatic protection circuit in a peripheral Part of the semiconductor substrate (12, 20) is formed in a staggered arrangement. 16. A method of manufacturing a semiconductor device according to one of claims 9 to 15, characterized in that the first diffusion layer is an N layer by means of implantation of phosphorus ions and the second diffusion layer (30) and the diffusion layer of the electrostatic Protective layer (31) can be formed as N-layers by means of an implantation of arsenic ions. BATH ORIGINAL