GB2186426A - Semiconductor device and method of fabrication thereof - Google Patents

Semiconductor device and method of fabrication thereof Download PDF

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Publication number
GB2186426A
GB2186426A GB08702881A GB8702881A GB2186426A GB 2186426 A GB2186426 A GB 2186426A GB 08702881 A GB08702881 A GB 08702881A GB 8702881 A GB8702881 A GB 8702881A GB 2186426 A GB2186426 A GB 2186426A
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region
doped
circuit
doped region
gion
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GB08702881A
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GB8702881D0 (en
GB2186426B (en
Inventor
Hidetoshi Iwai
Kazumichi Mitsusada
Masamichi Ishihara
Tetsuro Matsumoto
Kazuyuki Miyazawa
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical

Abstract

A semiconductor device has an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate (20). The internal circuit includes MIS elements and has a double-diffused drain structure (29, 30), while the protective circuit has a single-diffused drain structure (31, 32). The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors (31) and clamping MIS elements (32). The single-diffused drain structure of the protective circuit and the double-diffused drain structure of the internal circuit may be achieved by either scanning the ion implanting apparatus to avoid ion implantation into the region of the protective circuit, or forming a photoresist film over the region of the protective circuit to prevent ion implantation into the protective circuit region, during the formation of the first layer 29 of the double-diffused drain structure. <IMAGE>

Description

GB 2 186 426 A 1 SPECIFICATION tionthroug h the circuit 9 is shown in
Figure 3 of the accompanying drawings. A P-type silicon semi Semiconductor device and method of fabrication conductor su bstrate 12, has an isolation Si02 fi 1 M 13, thereof a resistor 10, a clamping MOSFET 11, a source region 70 14, a gate oxide fi 1 m 15, a gate electrode 16, a The present invention relates to a semiconductor de- phosphosilicate glass (PSG) fil m 17 and 18 an alumi vice having two circuits on the same semiconductor nium electrode formed thereon. Both the diffused re substrate and to a method of fabrication of such a sistor 10 and the semiconductor regions of the circuit. source and drain regions of the clamping MOSFET Miniaturisation of semiconductor devices (ICs) has 75 11 have a double- diffused drain structure, and con- been attempted to increase their operating speed sist of an N'-type layer and an W-type layer.
and improve their integration density. MOS el- In the semiconductor device of this kind, however, ements (MOSIFETs), which are typical examples of destruction of the insulating film of a MISFETfor MIS elements (MISFETs), are no exception. To mini- ming a firststage inverter and having a doubleaturise MOS elements, the thickness of theirgate 80 diffused drain tendsto occur. This is becausethe oxidefilms has been reduced and the length of their backward breakdown voltage atthejunction of a channels has become shorter and shorter.This MISFET (Diode) and having a double-diffused drain meansthat a relatively strong electricfield is gener- rises, the electrostatic energy is applied to the in ated within the device, so that injectin of hotcarriers sulating film before it can leakto a substrate by into the gate oxide film occurs, and thethreshold vol- 85 breakdown of the clamping MISFET.
tage shifts orthere is a degradation of mutual con- The present invention seeksto overcome, orat ductance. least ameliorate these problems, byforming a first A double-diffused drain structure such asthat circuit, e.g. an internal circuit such as a memory cell, shown in Figure 1 of the accompanying drawings with a double-diffused drain structure, and a second has been proposed to solvethese problems. Figure 1 90 circuit, e.g. the protective circuit,with a single is a section through a typical N-channel MOSFET. A diffused drain structure. The second circuit may be P-type silicon semiconductor substrate 1 has a sil- an electrostatic protective circuitwhich, as men icon dioxide (Si02) film 2, a gate oxide film 3 and a tioned above, protectsthe first circuitfrorn damage gate electrode 4formed thereon. In orderto reduce clueto abnormal external signals. Such a device re the strong electricfield in the proximity of the drain, 95 duces degradation of characteristics dueto hot car both drain and source have a double-diffused drain riers, and also reduces degradation of the destruc structure consisting of an W-type layer 5 of phosph- tion voltage. In this waythefield intensity acting orous (P) and an W-type layer 6 of arsenic (As) (refer upon the gate oxidefilm of e.g. a clamping MOSFET for example to the aricle by E. Takeda, et al, entitled may be reduced.
"An As-P (N + - N) Double Diffused Drain MOSFET 100 The present invention also proposes a method of for VLSI's", published in the Digest of Technical fabricating such a semiconductor device by forming Papers, Symp. on VLSI Technology, OISO, Japan, a first diffusion layer forthe first circuit and subsequ pp. 40-41 (Sept. 1982)). entlyforming a second diffusion layerforthe first cir Aprotective circuit is usuallyformed on the same cuitand a diffusion layerforthe second circuit. Inthis semiconductor substrate to protectthe MIS element 105 way the first circuit is provided with a double from abnormal signaisfrom outsidethe IC. As diffused drain structure whilst the second circuit has shown in Figure 12 of the accompanying drawings, a single-diffused structure.
the protective circuit (e.g., electrostatic protective Thetwo diffusion layers of thefirst circuit may be circuit) is a circuitto preventthe destruction of the formed either byfirst masking the second circuitfor gate insulating film of a MISFET71 of a firststage 110 the formation of thefirst diffusion layer, and then re inverter 68, the gate electrode of which is connected moving the mask, or by selective ion implantation to a bonding pad 8 through a resistor 10. Destruction scanning.
occurs when electrostatic energy is applied to the Embodiments of the invention will now be descri bonding pad. bed in detail, bywayof example,with referenceto Acircuitsuch asthat represented bythe equivalent 115 the accompanying drawings, inwhich:
circuitcliagrarn of Figure2 ofthe accompanying Figure 1 is a section through an N-channel MIS el drawings is a typical protective circuit9 used for pro- ementwith a double-diffused drain structure and has tecting circuits otherthan the protective circuit, e.g. already been described; an internal circuit of an IC. A signal to the internal Figure2is an electric equivalent circuit diagram of circuit is applied to a bonding pad 8through a diffu- 120 an example of an electrostatic protective circuitand sion resistor 10, one end of which is connected to the has already been described; pad 8, and a clamping MOSFET 11 whose gate and Figure 3 is a section through a device correspond source are earthed is connected to the junction be- ing to the equivalent circuit of Figure 2 and has tween the resistor 10 and the internal circuit. already been described; The inventors of the present invention have prod- 125 Figure 4 is a plan view of an example of the chip uced sample semiconductor devices of a doublepattern of a DRAM provided with an electrostatic diffused drain structure, and have discovered the foi- protective circuit and an internal circuit on the same lowing problem. semiconductor substrate; In this semiconductor device, the protective circuit Figures 5to Bare sectio ' nsthrough a semiconduc- 9 has also a double-diffused drain structure. A sec- 130 tor device, showing the fabrication method in accor- 2 GB 2 186 426 A 2 dance with one embodiment of the present inven- structure consisting of polycrystal line silicon and the tion; silicide of a metal with a high melting point. The cir Figures9and 10 are schematic plan views cor- cuit shown in Figure 2 illustrates an example of the responding to the electrostatic protective circuit and protective circuit on the left of figure 5, and the the internal circuit of Figure 8, respectively; 70 memory cell of the DRAM is shown as one example Figure 11 is a graph of experimental results show- of an internal circuit on the right of Figure 5.
ing the dielectric breakdown voltage of an electro- Athick oxide film 23 providing isolation is formed static protective circuitwith a single-diffused drain by selective thermal oxidation of the surface of the structure, compared with that of an electrostatic pro- silicon substrate 20, for example. A silicon nitride tective circultwith a double-diffused drain structure; 75 (Si3N4) film 25 acting as a dielectricfilm of a storage Figure 12is a circuitcliagram showing an electro- capacitor isformed on the surface of thefield oxide static protective circuit and a specific internal circuit film 23 on the memory cell side, and also on the sur protected thereby; face of a thin Si02 f ilm 24 that continues f rom the f i Im Figures 13and 14 are respectively circuit diagrams 23. A polycrystal 1 ine silicon electrode 27 is formed showing the present invention appi ied to a MISFET 80 on the thin fil m 25 through an Si02 film 26 and is composing a f irst stage of an in put buffer and a diffused with e.g. phosphorus ions so as to reduce its MISFETcomposing a final stage of an output buffer. resistance. The conductive layerwhich is the first Figures 15,16, and 17show circuit diagrams of layer consisting of this polyerystalline silicon elec CIVIISICS embodying the present invention; and trode 27 forms one of the electrodes of the capacitor Figure 18is a cross sectional view of part of the 85 of the memory cell. Ion implantation for an inversion circuit of the circuit of Figure 15 according to a first prevention layer (that is, a channel stopper layer), or arrangement; and for controlling thethreshold voltage, etc., has Figure 19is a cross sectional view of part of the already been completed bythis stage.
circuit of Figure 15 according to a second arrange- Next, as shown in Figure 6, a photoresistfilm 28 is ment. 90 selectively formed overthe surface of the protective Afirst embodimentof a semiconductor device and circuitalone, by a photolithographic process. More a method of fabricating it in accordancewith the pre- specifically, the photoresistfilm 28 (1 jim) isformed sent invention will now be described with reference only overthe region A in Figure 4. Ion implantation is to Figures 4to 10. However, such description ex- then effected using this photoresistfilm 28 as a emplifies, not limits the invention. 95 mask, in orderto form W-type diffusion layers 29 Figure 4 shows an example of the layout of a chip 7 which act as source and drain regions in the memory of a dynamic random access memory (DRAM) in ac- cell. This ion implantation uses phosphorus ions as cordance with one embodiment of the invention. The the N-type impurity, for example. The impurity dose DRAM consists of bonding pads 8, a protective cir- is 1 X 10141CM2 and the implantation energy is 50 KeV.
cuit 9 provided for each bonding pad 8, a signal gen- 100 Arsenic ions can be used as the impurity.
eration circuit 100 which generates read and write Referring to Figure 7, the photoresistfilm 28 is re- timing signals, etc., a memory array 101 in which moved, and then N-type impurity ions such as MIS elements are used as memory cells, and column arsenic ions are implanted to form an W-type layer and row decoders 102. 30, and hence a double-diffused drain structure. This Figures 5 to 8 are cross-sectional views showing, 105 ion implantation also forms a diffusion resistance step-by-step, the process of fabricating a semi- layer 31 of the protective circuit, as well as a source conductor device being an embodiment of the pre- drain region 32 of the clamping MOSFET. The im sent invention. The protective circuit is shown on the purity dose is 8 x 10151CM2 and the implantation en left of each drawing and a memory cell, which is part ergy is 80 KeV. Phosphorus ions can be used asthe of the internal circuit, is shown on the right. Figure 8 110 impurity.
is a section through a completed semiconductor de- As can be appreciated, the diffusion resistor can be vice, and Figures 9 and 10 are schematic plan views formed from a polysilicon layer, e.g., formed over of the semiconductor device of Figure 8. the semiconductor substrate.
Figure 5 shows the state in which the process has As can be seen from Figures 6 and 7, the protective been completed up to the formation of the gate elec- 115 circuit has a single-diffused drain structure while the trode of the MOSFET of the DRAM. This state may be internal circuit (memory cell) has a double-diffused completed by conventional techniques shown in drain structure. In this case, the photoresistfilm 28 is Figure 5 are a semiconductor substrate 20, a gate selectively formed to preventthe implantation of the oxide film 21, and a gate electrode 22. The semi- W-type phosphorus ions into the protective circuit.
conductor substrate 20 is, e.g., a P-type mono- 120 However, the implantation of phosphorus ions into crystalline silicon substrate having a (100) crystal the protective circuit can also be prevented by con plane, for example, and the gate oxidefilm 21 is an trolling the scanning of the ion implantation (by Si02 film, for example. The gate electrode 22 is a con- avoiding scanning of the region including the prot ductive layerforming a second layer, and is formed ective circuit, i.e., region A in Figure 4). This is re- by depositing polyerystalline silicon by chemical 125 latively easy because the electrostatic protective cir vapour deposition (CVD), and then diffusing e.g. cuit is usuallyformed in a certain region around the phosphorous ions to form polycrystalline silicon of a periphery of the chip, as shown in Figure 4, and so reduced resistance, The gate electrode may consist inhibitthe ion implantation may be limited by avoid of a layer of a metal which has a high melting point, a ing scanning this region..
layer of the silicide of such a metal, or a two-layered 130 After the electrostatic protective circuit of the 3 GB 2 186 426 A 3 single-cliffused drain structure and the internal cir- vice of this invenfflon can be easily fabricated by cuit of the double-diffused drain structure havethus adding only one photolithograpahic step.
been formed, a phosphosilicate glass film (PSG film) If alternatively a method is used of locally con 33 and an aluminium layer acting as a third conduct- trolling the ion implantation scanning to avoid the ive layer areformed as shown in Figure 8. The alumi- 70 protective circuit,the present invention can be exec nium layeracts as an output electrode 34forthe dif- uted by a simple production process.
fusion resistor31, an output electrode 35forthe Although the invention has been described specif internal circuit, a source electrode 36, and a data line icallywith referencto an em bodi ment thereof, the 37 of the memory cell. Afterthe PSG film 33 is present invention is not limited thereto, but can be formed, photoetching is used to form contact holes 75 modified in various ways. For example,the protect forthese electrodes, and aluminium sputtering is ive circuit in the embodiment described above con doneto form the electrodes. Finally, a PSG film 38 is sists of one diffused resistor and one clamping formed as a protective film. MOSFET, butthis is not necessary, and the invention Figures 9 and 10 are schematic plan views of the can be applied to various protective circuitsthat electrostatic protective circuit and internal circuit of 80 utilize the junction breakdown in a diffusion layer Figure 8, respectively. Asection along the line B - B of andthe surface breakdown atthe drain end of a Figureg and a section along the line C-C of Figure 10 clamping MOSFETto improvethe dielectric break correspondto the protective circuit region andthe down voltage. Moreover, the clamping MOSFETcan internal circuit region of Figure 8, respectively. be replaced by one ortwojunction diodes. In this In Figure 9 is shown a bonding pad 40, a diffusion 85 case, thejunction of the diode is between the P-type layer41 foran input portion, a contact hole 42, and a substrate and the W4type layerformed simu diffused resistor43. Also shown is a clamping ltaneously with the N -type layers 30,31 and 32.
MOSFET 44 which consists of a reg ion 45 con nected Similarly, a DRAM has been described as an ex electricallyto the diffused resistor43, a gate elec- ample of the internal circuit, butthe internal circuit is trode 46 and a source 47. The region 45 is connected 90 not limited to a DRAM, and the invention may be to an aluminium signal line 4513through contacts applied to other circuits provided with MIS elements 45A, and the aluminium signal line 45B is electrically which have at least a double-diffused drain structure.
connected to the internal circuit. Similarly,the Thus,the present invention can be embodied in a source 47 is connected to an aluminium line 47B MISFET having a single- diffused drain structure, through contacts 47A, and one end of the aluminium 95 applied to a MISFETforming thefirst stage of an line 47B is connected to the gate electrode through a input bufer and to a MISFETforming a final stage of contact^with the other end earthed. an output buffer. Circuit diagrams for such MISFETS In Figure 10, a boundary line 50 of the field oxide having the single- diffused structure, applied to the film def ines the active region of the memory cell, and MISFETforming the first stage of an input buffer and a polycrystalline silicon word line 51 correspondsto 100 the MISFETforming the final stage of an output buf the gate electrode of the MOSFET. Polyerystalline sil- fer are shown in Figures 13 and 14. In Figures 13 and icon 52 acts as one of the electrodes of the capacitor 14, respectively, there are shown an input pad 81 and of the memory cell, and an aluminium electrode 53 is an output pad 82, and the structure within dotted wired to a contact hole 54 of the data line. lines 83,84 represents the single-diffused drain Figure 11 is a graph of typical experimental data 105 structure.
comparing the electrostatic destruction voltage of a Moreover,the invention may also be applied to N protective circuitwith a single-diffused drain struc- channel MISFETs of a CIVIISIC,where N-channel ture and that of a protective circuitwith the double- MOSFETs areformed in a P-well region or a P diffused drain structure. The percentage accumulatsubstrate.
ive defect ratio is shown along the ordinate, and the 110 Figures 15,16 and 17 showthe circuit diagramsfor electrostatic destruction voltage (V) along the such a CMISIC. The structure within dotted lines 85, abscissa. The segmented line a denotes the data 86 and 87 has a single- diffused drain structure. The from devices having a double-diffused drain strucstructures of the MISFETS 88,89 and 90 in Figure 15 ture, and the segmented line b data from the devices are shown in more detail in Figure 18. The N-channel having a single-diffused drain structure. The voltage 115 MISFET 89 has a double diffused drain structure with resistance of the same pin of five samples was ex- an W-type layer 58 and W-type layer 59, which are amined. It can be seen from the graph that a protect- formed in a P-type substrate 56. P'-type regions 61 ive circuitwith a single-diffused drain structure exhi- act as source and drain regions of the P-channel bits a much better electrostatic destruction voltage. MISFET 90 formed in an W-type well region 57. The As described above, since the protective circuit 120 MISFET88 has a single diffused drain structure with has a single-diffused drain structure and the internal an W-type layer 60 formed in the substrate 56. A circuit has a double-diffused drain structure,the el- diode91 has a same structure as the MISFET 88. Jun ectric field concentration in the internal circuit and ction diodes 93,94 (Figure 16) 96 and 97 (Figure 17) the electricfield concentration in the gate oxidefilm areformed between a P-type substrate and W-type of the firststage MISFETof the internal circuitcan be 125 layers such asthe W-type layers 60 shown in Figure reduced, ameliorating the problems of hot carriers 18. The W-type layers 60 are drains of MISFETS and and of destruction voltage. are formed simultaneously. If a resistor 92 is made of Since a mask is applied to the protective circuitto an N ±type layer, e. g. si m u ltaneously with layers 60, preventthe formation of one of the diffusion layers the diode 94 can be formed parasitically between the of the double-diffused drain, the semiconductor de- 130 resistor 92 and the P-type substrate 56.
4 GB 2 186 426 A 4 Moreover,the invention can be applied to devices 7. A semiconductor device according to anyone in which the N-channel MISFETS 91 have the struc- of the preceding claims, wherein the first doped re ture shown in Figure 19. The source and/or drain re- gion is within the second doped region.
gion of the MISFET 91 is formed by an W-type layer 8. A semiconductor device according to anyone 64 formed in self-alig n mentwith agate electrode 65 70 of claims 1 to 6, wherein the first and second doped and an N'-type layer 63 formed in self-alignment regions are adjacent each other.
with a side wall spacer62 and the gate electrode 65. 9. A semiconductor device substantially as The MISFET 91 replaces the MISFET 89, for example. herein described with reference to and as illustrated Thus, while the foregoing description has been dir- in Figure4, or Figures 5to 10, oranyone of Figures ected to a DRAM and its protective circuit, the pre75 15 to 19.
sent invention may be applied to ordinary MOS in- 10. A method of fabricating a semiconductor de- tegrated circuits such as DRAMS (e.g., 256 K bits vice having at least one MISFETfor a first circuit and DRAMS), SRAMs, MOS logic circuits, and so forth. a protective element of a second circuit electrically Whilewe have shown and described embodi- connected to thefirst circuitfor protecting thefirst ments of the present invention, itshould be under- 80 circuitfrom an external surgevoltage introduced stood thatthe invention is not limited thereto but is through an external terminal, thefirst and second cir susceptible of numerous changes and modifications cuits being formed in a major surface of a semi as is apparentto one having ordinary skill in the art conductor substrate; and wetherefore do notwish to be limited to the det- the method including; ails shown and described herein. 85 forming by diffusion first and second doped re gionsforthe at leastone MISFET,thefirst doped re

Claims (8)

  1. CLAIMS gion being of high concentration and the second doped region being
    of relatively low concentration, 1. A semiconductor integrated circuit device, of the same conductivity type as the first doped re- formed in a major surface of a semiconductor sub- 90 gion, and being in contact with the first doped re strate, having at least one M ISFETfor a first circuit, gion; and the atleastone MISFEThaving a diffused drain re- forming by diffusion a doped region of the protect gion, each drain region of the at least one MISFET ive element, the doped region being formed simu comprising a first doped region of high concentra- ltaneously with thefirst doped region and having a tion and a second doped region of relatively low con- 95 high concentration substantiallythe same asthe first centration of the same conductivity type as the first doped region; doped region, and in contactwith thefirst doped re- wherein no region of the protective element is gion, wherein a protective element of a second cir- formed which has a concentration and conductivity cuit electrically connected to thefirst circuitfor prot- type substanitallythe same asthe second doped re ecting the first circuitfrom an external surge voltage 100 gion and which is in contact with the region of high introduced through an external terminal, has a concentration of the protective element.
    doped region of a high concentration substantially 11. A method according to claim 10, wherein a the same as the first doped region and of the same maskis formed over the second circuit prior to the conductivity type and no region having a concentra- formation of the second doped region, andthe mask tion and conductivity type substantiallythe same as 105 is removed afterthe formation of the second doped the second doped region and which is in contactwith region but beforethe formation of the first doped re the region of high concentration of the protective el- gion.
    ement, wherein the region of high concentration of 12. A method according to claim 11, wherein said the protective element is formed simultaneously maskis madefrom a photoresistfilm.
    with the dirst doped region. 110 13. A method according to claim 10, wherein the
  2. 2. A semiconductor device according to claim 1, second diffused region is formed by ion implantation wherein the first circuit is an internal circuit, and the scanning over onlythe first circuit, and the first dif second circuit is an electrostatic protective circuit. fused region and the region of high concentration of
  3. 3. A semiconductor device according to claim 2, the protective element are formed by ion implantawherein the electrostatic protective circuit includes 115 tion scanning overthe entire surface of the device.
    at least one diffused resistor and at least one clam- 14. A method according to anyone of claims 10 ping MIS element. to 13, wherein thefirstcircuit is an internal circuit,
  4. 4. A semiconductor device according to claim 3, and second circuit is an electrostatic protective cir wherein the diffused resistor has a high concentra- cuit.
    tion substantiallythe same as the first doped region 120 15. A method according to anyone of claims 10 and no region which has a conductivity type and con- to 14, wherein thefirst and second doped regions, centration substantially the same asthe second and the doped region of high concentration of the doped region. protective element, are each formed by ion implanta
  5. 5. A semiconductor device according to claim 3 tion.
    or claim 4 having an input bonding pad, the resistor 125 16. A method according to claim 15, wherein the being electrically connected to the internal circuit second doped region is an N- layer formed by ion and to the bonding pad. implantation of phosphorous ions, and the first
  6. 6. A semiconductor device according to anyone doped region and the region of high concentration of of claims 2to 5,wherein the internal circuit has a the protective element are N' layersformed by ion dynamic RAM element. 130 implantation of arsenic ions.
    GB 2 186 426 A 5 17. A method according to anyone of claims 10 the method including; to 16, wherein the electrostatic protective circuit is forming by diffusion first and second doped re positioned at a peripheral portion of the semi- gions forthe drain region of the at least one MISFET, conductor substrate in an offset arrangement. the first doped region being of high concentration 18. A method according to anyone of claims 10 70 and being formed in self- aiig n ment with one of the to 17, wherein the first doped region is formed within side wall spacers and the gate electrode, and the the second doped region. second doped region being of relatively low con 19. A method according to anyone of claims 10 centration, of the same conductivity type as the first to 17, wherein the first doped region is formed adja- doped region, being in contact with the first doped cent the second doped region. 75 region, and being formed in self- alignment with the 20. A method of fabricating a semiconductor de- gate electrode; and forming by diffusion a doped re vice substantially as any one herein described with gion of the protective element, the doped region reference to Figures 4to 14 of the accompanying being formed simultaneously with thefirst doped re drawings. gion and having a high concentration substantially 21. A device formed bythe method of anyone of 80 the same as the first doped region; claims 9 to 18. wherein no region of the protective element is formed which has a concentration and conductivity Amendments to the claims have been filed, and type substantially the same as the second doped re have the following effect:- gion andwhich is in contactwiththe region of high (a) Claims 1, 7-21 above have been deleted or 85 concentration of the protective element.
    textually amended. 9. A method according to claim 8, wherein a (b) New or textually amended claims have been mask is formed over the second circuit prior to the filed as follows: formation of the second doped region, and the mask is removed afterthe formation of the second doped 1. A semiconductor integrated circuit device, 90 region but before the formation of the first doped re- formed in a major surface of a semiconductor sub- gion.
    strate, having at least one MISFETfor a first circuit, 10. A method according to claim 9, wherein said the at least one MISFET having a diffused drain re- mask is made from a photoresistfilm.
    gion, and agate electrode with side wall spacers on 11. A method according to claim 8, wherein the either side of the gate electrode, each drain region of 95 second diffused region is formed by ion implantation the at least one MISFET comprising a first doped re- scanning over only the first circuit, and the first dif gion of high concentration and a second doped re- fused region and the region of high concentration of gion of relatively low concentration of the same con- the protective element are formed by ion implanta ductivitytype as the first doped region, and in tion scanning overthe entire surface of the device.
    contaetwith the f irst doped region, wherein a prot- 100 12. A method according to anyone of claims 8to ective element of a second circuit electrically connec- 11 wherein the first circuit is an internal circuit, and ted to the first circuitfor protecting the first circuit second circuit is an electrostatic protective circuit.
    from an external surge voltage introduced through 13. A method according to anyone of claims 8to an external terminal, has a doped region of a high 12,wherein thefirst and second doped regions, and concentration substantiallythe same asthefirst 105 the doped region of high concentration of the prot doped region and of the same conductivity type and ective element, are each formed by ion implantation.
    no region having a concentration and conductivity 14. A method according to claim 13, wherein the type substantially the same as the second doped re- second doped region is an N -layer formed by ion gion and which is in contact with the region of high implantation of phosphorous ions, and the first concentration of the protective element, wherein the 110 doped region and the region of high concentration of region of high concentration of the protective el- the protective element are N' layers formed by ion ement is formed simultaneously with the first doped implantation of arsenic ions.
    region, and wherein the second doped region is 15. A method according to anyone of claims 8to formed in self-alignment with the gate electrode, and 14, wherein the electrostatic protective circuit is posi the first doped region is formed in self-alignment 115 tioned ata peripheral portion of the semiconductor with one of the side wall spacers and the gate elecsubstrate in an offset arrangement.
    trode.
  7. 7. A semiconductor device substantially as herein described with reference to and as illustrated in Figure 19. Printed for Her Majesty's Stationery Office by Croydon Printing Company (UK) Ltd,6187, D8991685.
  8. 8. A method of fabricating a semiconductor de- Published byThe Patent Office, 25 Southampton Buildings, London,WC2A lAY, vice having at least one MISFETfor a first circuit, the from which copies maybe obtained.
    at least one MISFET having a diffused drain region and agate electrode with side wall spacers on either side of the gate electrode and a protective element of a second circuit electrically connected to the first cir cuit for protecting the first circuit from an external surge voltage introduced through an external ter mina 1, the first and second circuits being formed in a major surface of a semiconductor substrate;
GB08702881A 1983-12-26 1987-02-09 Semiconductor device and method of fabrication thereof Expired GB2186426B (en)

Applications Claiming Priority (1)

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JP58243801A JPH0646662B2 (en) 1983-12-26 1983-12-26 Semiconductor device

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GB8702881D0 GB8702881D0 (en) 1987-03-18
GB2186426A true GB2186426A (en) 1987-08-12
GB2186426B GB2186426B (en) 1988-01-06

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GB08432417A Expired GB2152284B (en) 1983-12-26 1984-12-21 Semiconductor device and protective circuit
GB08702881A Expired GB2186426B (en) 1983-12-26 1987-02-09 Semiconductor device and method of fabrication thereof

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KR (1) KR930001564B1 (en)
DE (1) DE3446928A1 (en)
FR (1) FR2561042B1 (en)
GB (2) GB2152284B (en)
HK (2) HK41790A (en)
IT (1) IT1179545B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0516146A1 (en) * 1991-05-29 1992-12-02 Nec Corporation Semiconductor integrated circuit having improved protection element
GB2274203A (en) * 1993-01-07 1994-07-13 Seiko Epson Corp Semiconductor device protection

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62169468A (en) * 1986-01-22 1987-07-25 Nec Corp Semiconductor integrated circuit device
JPS63119574A (en) * 1986-11-07 1988-05-24 Toshiba Corp Manufacture of semiconductor device
US5183773A (en) * 1989-04-13 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device including such input protection transistor
US5142345A (en) * 1989-04-13 1992-08-25 Mitsubishi Denki Kabushiki Kaisha Structure of input protection transistor in semiconductor device including memory transistor having double-layered gate and method of manufacturing semiconductor device including such input protection transistor

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US373249A (en) * 1887-11-15 Clock
GB1170705A (en) * 1967-02-27 1969-11-12 Hitachi Ltd An Insulated Gate Type Field Effect Semiconductor Device having a Breakdown Preventing Circuit Device and a method of manufacturing the same
US3999212A (en) * 1967-03-03 1976-12-21 Hitachi, Ltd. Field effect semiconductor device having a protective diode
DE2545871B2 (en) * 1974-12-06 1980-06-19 International Business Machines Corp., Armonk, N.Y. (V.St.A.) Field effect transistor with improved stability of the threshold voltage
NL176322C (en) * 1976-02-24 1985-03-18 Philips Nv SEMICONDUCTOR DEVICE WITH SAFETY CIRCUIT.
DE2940954A1 (en) * 1979-10-09 1981-04-23 Nixdorf Computer Ag, 4790 Paderborn METHOD FOR THE PRODUCTION OF HIGH-VOLTAGE MOS TRANSISTORS CONTAINING MOS-INTEGRATED CIRCUITS AND CIRCUIT ARRANGEMENT FOR SWITCHING POWER CIRCUITS USING SUCH HIGH-VOLTAGE MOS TRANSISTORS
US4342045A (en) * 1980-04-28 1982-07-27 Advanced Micro Devices, Inc. Input protection device for integrated circuits
JPS5715459A (en) * 1980-07-01 1982-01-26 Fujitsu Ltd Semiconductor integrated circuit
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
JPS57188364U (en) * 1981-05-25 1982-11-30
JPS57211272A (en) * 1981-06-23 1982-12-25 Toshiba Corp Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0516146A1 (en) * 1991-05-29 1992-12-02 Nec Corporation Semiconductor integrated circuit having improved protection element
US5449940A (en) * 1991-05-29 1995-09-12 Nec Corporation Semiconductor integrated circuit having improved protection element
GB2274203A (en) * 1993-01-07 1994-07-13 Seiko Epson Corp Semiconductor device protection
GB2274203B (en) * 1993-01-07 1996-08-07 Seiko Epson Corp Semiconductor device
US5614752A (en) * 1993-01-07 1997-03-25 Seiko Epson Corporation Semiconductor device containing external surge protection component

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HK48090A (en) 1990-06-29
GB2152284A (en) 1985-07-31
IT1179545B (en) 1987-09-16
FR2561042B1 (en) 1988-11-10
IT8424246A0 (en) 1984-12-24
GB8702881D0 (en) 1987-03-18
FR2561042A1 (en) 1985-09-13
KR850005166A (en) 1985-08-21
DE3446928A1 (en) 1985-07-04
HK41790A (en) 1990-06-08
GB8432417D0 (en) 1985-02-06
JPH0646662B2 (en) 1994-06-15
GB2152284B (en) 1988-01-06
GB2186426B (en) 1988-01-06
KR930001564B1 (en) 1993-03-04
JPS60136374A (en) 1985-07-19

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