GB2132042A - Frequency and timing sources - Google Patents

Abstract

A frequency or timing source comprises a stable oscillator 31, a programmable divider 32, and a comparator 36 which receives the divider output and also an intermittent external reference. In the presence of the external reference an error determination is made and applied to a controller 34 which includes a memory section. From the error the controller determines the amount by which the divider must change its division ratio to remain in synchronism with the reference in the future. Thus the system learns how to improve its operation. If the response of the oscillator to temperature changes is known, a measure of temperature can also be applied to the controller 34 for appropriate compensation in the divider 32; alternatively this compensation can be learnt by correlating the temperature with the correction applied. An improved binary rate multiplier is also disclosed (Figures 4-7). <IMAGE>

Description

SPECIFICATION Frequency and timing sources The present invention relates to frequency sources and timing sources incorporating them - and more particularly to controlling the frequency thereof to remain in step with an external reference source which is not always available.

Synchronisation to an external source is of course well known, for example using a phase locked loop arrangement, where the phase of a controllable oscillator is continuously compared with that of a reference, and the error used as a feedback signal to control the oscillator frequency. This arrangement, however, requires the reference to be continuously available.

The use of an occasional reference is also known: for example the act of occasionally (but not necessarily regularly) resetting one's watch to a time signal. It is, for example, known to reset a digital watch by pushing a button 'on the minute' which then resets the internal counters to the nearest minute, correcting a cumulative error of up to 30 seconds. This corrects the accumulated error of the watch, but does not improve its time-keeping, however.

The present invention is defined in the appended claims to which reference should now be made.

The invention in its various aspects will be described in more detail with reference to the drawings, in which: Figure lisa block circuit diagram of a digital watch embodying the invention; Figure 2 is a block circuit diagram of a frequency source embodying the invention; Figure 3 is a diagram illustrating the nature of successive corrections in operation of the frequency source of Figure 2; and Figures 4 to 7 illustrate successively improved forms of binary rate multiplier for use in the circuit of Figure 1 or Figure 2.

Figure 1 shows a clock circuit 10 such as in a digital watch, having a stable fixed frequency oscillator 12.

The oscillator supplies a high frequency signal f0 to a programmable divider 14 which divides down to give pulses at a rate corresponding to the greatest degree of accuracy required, e.g. at intervals of one second or one tenth of a second. These pulses are applied to an accumulator 16 which counts up the received pulses to give the current time which is applied to the watch display 18.

A comparator 20 is used in conjunction with a reset or reference input 22 to determine the error in the displayed time at periodic intervals. This error is applied to a controller circuit 24 which includes a memory. The controller can work in various ways.

For example, if the reference input 22 automatically corrects the value in the accumulator 16, then the controller 24 simply has to work out the rate at which the error developed and directly apply a correction.

That is to say, the controller 24 should determine the time period since the last correction was made, determine the error which has accumulated in the meantime, and hence calculate the error rate. This is corrected for by adjusting the divider circuit 14 to divide by a slightly different factor.

Alternatively, where a sudden jump in the display ed output is undesirable, the controller works in two phases. The error rate is calculated as before, but in the first phase the error rate is overcompensated by a predetermined amount to allow the clock to 'catch up' and remove the accumulated error. After this, in the second phase the compensation is maintained at a value necessary to keep the clock accurately in time. The appropriate division ratio is then stored in the memory in the controller 24.

In either event it will be seen that a fixed stable oscillator can be used as it is the division ratio of divider 14 which is altered, not the output of the oscillator 12.

Although shown as two circuits, the divider 14 and accumulator 16 may be closely integrated with each other, both forming part of the same overall circuit element.

Reference is now made to Figure 2 which shows a fixed frequency source. A stable local oscillator 31 has an output frequency f0 which is divided by a programmable divider (or counter) 32 to give the desired output frequency f2. It is assumed that an external reference frequency f1 is available from time to time at input 33. When available, it is compared in a comparator 36 with the output f2 and the result of the comparison (i.e. the error Af2 in the output) is used by a controller 34 to alter, in a systematic way, the division ratio of the divider 32.

The controller 34 includes a memory so that this alteration is effective for as long as is necessary (i.e.

until the next reference). The logic within the controller would be such as to be resistant to transient disturbances, in particular the correction currently being applied to the programmable divider would preferably be stored in a non-volatile memory so that only second-order corrections would need to be made following a powerfailure.

In some applications (e.g. burst-locked oscillator for television decoding) the external information is available sufficiently often for the controller to adapt to long-term influences such as the drift in the reference source frequency with change in ambient temperature. In other cases (the maintained clock required to 'freewheel' for several days) it would be useful to make information about these influences available to the controller. For example, as indicated in Figure 2, a sensor 35 to monitor the temperature of the reference source could be connected to the controller.Known information about the variation of the reference source frequency with temperature could be provided within the controller 34, but it could alternatively be provided that the controller 'learn' this information itself, and to update it once learnt, by correlating the required correction with the output of the temperature sensor.

Note that the locally generated signal f2 need not be at the same frequency as the external reference f1, provided that there is an integer ratio between them. Similarly 2 need not be an integer division of fO. Techniques for counting and comparing frequencies in the ratio p:q, where p and q are integers are described in British Patent 1,455,821. For example if f0 were nominally 10 MHz and f1 were nominally 10 Hz, but not strictly related to fO, f0 could be divided by 976 or 977, and this then divided by 1024, to give f2.

The controller would alter the pattern of division by 976 or 977 to give the effective ratio required to keep f2 in track with f1. In the steady state there would be a regular pattern of 7 divisions by 976 interleaved with 9 divisions by 977 to give an overall division by 1,000,000. The small changes in phase required to keep in track would involve occasional and substantially regular disturbances to this pattern. The changes to the pattern would probably be stored as first, second and perhaps higher-order events occurring less and less frequently (c.f. every 4th year is a leap year unless it is one of every 100th which is not unless again it is one of every 400th which is).

There may be more than one component of the external reference to be compared, for example the 60kHz MSF standard frequency transmissions are amplitude modulated by 1 Hz pulses. This applies where the external source has a regular structure comprising both coarse and fine detail. This makes it possible to make the comparison with precision without sacrificing the range of comparison. For example it would be possible to resolve one sixteenth of a cycle of a 60kHz standard frequency signal, corresponding to about one microsecond, but there would bea maximum peak-to-peak range of comparison of one cycle (about 16 microseconds), beyond which the cycle repeats and the comparison is ambiguous.If the standard frequency is amplitude modulated at 1 Hz, with the modulated signal coherent with the standard frequency (i.e. the signal repeats in every respect every second) then the comparison can still be made to one microsecond precision but the peak-to-peak range of comparison is extended to one second. Similarly, as in the case of example 3 below, synchronous transmissions at, say, 500kHz could carry low-level amplitude modulation at a sub-harmonic frequency, say 4kHz, in order to give a range of 250 microseconds (equivalent to 75km of distance) in order to give a range of 500kHz (equivalent to 600 metres). These equivalent distances are important to this example which relates to moving vehicles, as the movement of the receiver between comparisons reduces the effective nonambiguous comparison range.

It is felt that the technique outlined above will become increasingly important because a) it is easier to provide a stable fixed4requency source than a stable controlled-frequency source (e.g.

phase-locked loop with voltage-controlled oscillator). b) it is already practicable to provide nonvolatile memory using battery of even capacitor power supply, and electrically-alterable read-only memories (EAROM'S) are now becoming available.

c) the widespread availability of the microprocessor, coupled with its capacity for reprogramming, make it attractive as the controller in such a system.

In the case of the watch illustrated in Figure 1, it is seen that the watch would 'learn' from the amount of correction and the interval between corrections and then modify its internal counting in such a way as substantially to reduce the magnitude of subsequent corrections and/or the frequency with which they will be needed.

Some examples of situations in which the technique may be applied are thus summarised as: 1) Synthesising a colour subcarrier in a digital television system by reference to an external colour burst; (i.e. not under local control, as would be the case with television signals received from another organisation, or another country).

2) Maintaining a radio-data transmission locked to the 60kHz standard frequency and time transmissions during both scheduled and unscheduled outages of between one hour and two weeks duration.

3) Maintaining a time-reference in a moving vehicle between synchronous transmissions from different sites at different times on the same frequency as part of a navigation system using for example, the proposed CARFAX (Trade Mark) network.

4) Improving the time-keeping of a digital clock or wrist-watch by occasionally (but not necessarily regularly) injecting a time signal.

It is most probable that a control mechanism would in practice be based upon a microprocessor, so it is best described in terms of a decision list (flow diagram) which is applied to each particular case.

The control mechanism has inputs such as: 1) is the reference present? is it stable? 2) what is the current error (difference) from the comparator? 3) a time-base (which is conveniently the system output clock).

Within the controller is stored the control program software, together with the history of significant previous events (i.e. what previous errors were, how they were corrected, and when this was done). The program is all, or at least mostly, in permanent read-only memory and the history is, ideally, in 'non-volatile' memory (such as low-power read/ write memory with battery back-up power supply, or an electrically alterable read-only memory EAROM). The facility to compile a file of previous events, which can be referred to by the program (and even be used to change parts of the program in EAROM) gives the controller the essential ability to 'learn' and 'anticipate' trends in the behaviour of the stable oscillator vis-a-vis the intermittent reference.

The above description illustrates an example of division from 10MHzto 10Hz via a programmable divider by 976 or 977 coupled with a fixed divide-by1024. Depending on the control to the programmable divider the overall division ratio can be varied by just over one part in 103 peak-to-peak. The control signal, a two-level signal switching between the two division ratios, is in this example updated at a rate of 1024Hz. The control signal can be the output of an 'improved binary rate multiplier' described below, which can produce m pulses as regularly spaced as possible within 2m clock pulses (c.f. British Patent 1,455,821). This device stores a binary control number which is revised from time to time by the controller. There is little difficulty in extending the size ofthe control number to give any desired precision, for example a 32-bit number would give a resolution of better than 2.5 parts in 1010 in the control sequence, and better than 2.5 parts in 1013 in the overall division. This resolution is comparable to the long-term stability of the very best oscillators available.

The principal output of the controller is this control number, other outputs are diagnostic in order to communicate the current status and reliability of the device to the user (e.g. a message "a reference has not been available for over 1000 hours").

Within the controller, the program examines the inputs and decides, on the basis of criteria provided initially or 'learnt by experience', whether the reference is present, and whether it is consistent and believable. It then decides whether the error indicated by the comparator is significant, and whether it is consistent and believable. The decision on whether the error is significant depends on the predicted effect of the most recent corrective action.

A typical strategy for error correction which is designed to minimise accumulated error is indicated in Figure 3. The long-term trend can be found (with respect to an arbitrary reference) by subtracting the integrated effect of the corrections so far from the observed error, and dividing by the total time. The correction can take the form of an asymptotic approach to the trend line, with a time-constant comparable to the total time so far. This process can be modified by attaching less weight to events long past, in order to compensate for ageing of the oscillator, or by modelling the ageing itself as a polynomial in time at + bt2 + ct3 rather than simply as a linear trend.

An 'improved binary rate multiplier', as mentioned above and used to provide a control signal, will now be described. What has to be achieved is a division where the ratio is expressed as a binary number in the range 0 to 1 with any required degree of precision. Unlike the system described in our British Patent 1,455,821, this new method allows the precision to be increased indefinitely without affecting the maximum operating speed of the logic. This is because the information flows only one way (rather than round a loop), so it is possible to partition the process into a 'pipeline' operation.The disadvantage is that it only applies exactly to division by a ratio of the form m/2", i.e. a non-recurring binary number, so it could not, for example, operate continuously in the ratios given as example in the above British Patent, as there would be a cumulative error increasing with time. However, in the present instance the ratio is capable of variation in a controlled way and any systematic error is accommodated in the closedloop control.

The technique is illustrated in the Figures 4 to 7.

Figure 4 shows the combination of an 8-bit adder 40 and an 8-bit register 42 used to generate a sequence of, in this example, 38 output pulses in every 256 clock pulses, as described in British Patent 1,455,821 (to which reference should be made). The binary number added to the contents of the register is equivalent to the decimal number 38. The addition 'overflows' 38 times during every 256 clocks (because 256 x 38 = 38 x 256) so 38 'carries' are generated. This is, in fact, a special case of the technique described in British Patent 1,455,821. In the general case there is feedback from the delayed 'carry' output of the adder to modify the next added number, so allowing the operation to be modulo-Q, where Q is not a power or two. In this special case, because an n-bit register and adder inherently operate modulo-2", there is no feedback.

Figure 5 shows additional stages 50,52 in the adder/register combination to give improved precision in the counting ratio. In this example the decimal number 115 is added to the lower part, so that overall output is 38 215 38215165 pulses for every 256 master clocks, or 9 843 pulses, spaced as regularly as possible, for every 65 536 master clocks.

The improvement comes from the realisation that i) information only travels one way in this process, and ii) every register state is a valid state in the generator sequence. This means that any one or more (or even all) of the 'carry' paths can include a register stage in order to re-time (and delay) that data, without affecting the overall operation of the binary rate multiplier. So, as shown in Figure 6, three 8-bit stages could include carry delays between every four bits in order to improve the maximum operating speed with a given logic type (the critical path is usually the propagation of a 'carry' all along the adder).

The fastest implementation of the technique is indicated in Figure 7. It is clear that such an operation is ideally suited to integration, and that sub-units of n stages can readily be combined.

This new method has three significant advantages over the conventional 'Binary Rate Multiplier', a well-known device which has been embodied in integrated circuit logic such as the Texas Instruments' type number 7497. The first is that it produces an output which is as regular as possible, so, for example, three events in a 64-clock sequence could occur at counts of 21,42 and 63 giving intervals of 22, 21 and 21, whereas the Binary Rate Multiplier would produce events at counts of 16,32 and 48 giving intervals of 32, 16 and 16. The second is that it can be extended indefinitely in precision without any penalty of speed, as each additional stage is, in effect, just another stage in a shift register. The third is that it is easier to configure the component parts when they are combined for greater precision, they are simply wired together in a 'daisy chain'.

Claims (8)

1. A method of controlling a frequency or timing source in response to an intermittent reference, comprising comparing the output of oscillator means intermittently with an intermittently-received reference, calculating from the result of the comparison a correction required to correct the output of the oscillator means to tend to return it to synchronism with the reference, storing the calculated correction in a memory, and applying the stored correction to the oscillator means.

2. A method according to claim 1, in which the oscillator means includes a stable fixed frequency oscillator and a programmable divider, the stored correction being applied to control the division ratio ofthe divider.

3. A frequency or timing source for use in the method of claim 2, and comprising a fixed frequency oscillator, a programmable divider connected to the oscillator output, a comparator to compare the divider output with an intermittent reference, and a control circuit connected to the comparator output and having a memory section and also connected to control the division ratio of the divider and in the presence of an output from the comparator representing an error to change the division ratio in the sense so as to compensate for the error.

4. Atiming source for use in the method of claim land comprising oscillator means, an accumulator for counting up the output of the oscillator means, a comparator for comparing the accumulated count with an intermittent reference, and control means connected to the comparator output to determine the current mean error rate and to store and apply to the oscillator means a signal to change the oscillator means such as to tend to reduce the error.

5. A frequency source for use in the method of claim 2, and comprising a fixed frequency oscillator, a programmable divider connected to the oscillator output, a phase comparator to compare the divider output with an intermittent reference, and a control circuit connected to the comparator output and having a memory section and also connected to control the division ratio of the divider and in the presence of an output from the comparator representing an error to change the division ratio in the sense so as to compensate'for the error.

6. A source according to claim 3,4 or 5, including means operable to measure an external variable which has an effect on the oscillator means and to accumulate, upon repeated corrections, data upon the dependence of the error on the external variable, and to compute and, during intervals in which the reference is absent, to apply to the control circuit additional corrections related thereto.

7. A frequency or timing source substantially as hereinbefore described with reference to Figure 1 of the drawings.

8. Afrequency or timing source substantially as hereinbefore described with reference to Figure 2 of the drawings.