GB2127751A - Producing narrow features in electrical devices - Google Patents

Producing narrow features in electrical devices Download PDF

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Publication number
GB2127751A
GB2127751A GB08326620A GB8326620A GB2127751A GB 2127751 A GB2127751 A GB 2127751A GB 08326620 A GB08326620 A GB 08326620A GB 8326620 A GB8326620 A GB 8326620A GB 2127751 A GB2127751 A GB 2127751A
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GB
United Kingdom
Prior art keywords
feature
integrated circuit
narrow feature
narrow
intermediate layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB08326620A
Other versions
GB2127751B (en
GB8326620D0 (en
Inventor
Anthony Marsh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Priority to GB08326620A priority Critical patent/GB2127751B/en
Publication of GB8326620D0 publication Critical patent/GB8326620D0/en
Publication of GB2127751A publication Critical patent/GB2127751A/en
Application granted granted Critical
Publication of GB2127751B publication Critical patent/GB2127751B/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Fine line features are produced on for example a silica layer 1 by printing an oversized mask version e.g. composed of metal 3 of the feature on an intermediate layer e.g. a polymer layer above the layer on which the features are required and then overetching and thereby undercutting the oversized version to produce the fine lines. A further metal mask may be sputtered onto the remaining intermediate layer and following removal of the intermediate layer this may be used as the mask for the fine line features. The fine line features may be present in integrated circuit devices. <IMAGE>

Description

SPECIFICATION Improvements in or relating to integrated circuits The present invention relates to integrated circuit devices and small electronic devices produced by photoresist techniques and particularly to the production in such devices of extremely narrow features.
At present the optical replication performance of a typical machine such as a Perkin-Elmer 220 is around 1.5 ym and it is an object of the present invention to be able to utilise such a machine to produce features as narrow as 0.1 Mm.
According to the present invention there is provided an integrated circuit or similar small electronic device including a narrow feature in which the narrow feature is produced by printing an oversized version of the narrow feature on an intermediate layer situated on top of the material in which the narrow feature is required, said oversize version being in a substance which is not etched by a subsequent etching process which is used to undercut the oversized feature thus producing a narrow feature whose width depends on the amount of etching.
Preferably when the etching process has been completed a sputtered coat of metal is applied to the surface remaining and the remaining portion of the intermediate layer is removed. This sputtered coat of metal then forms a second mask which carries the narrow features as windows.
Embodiments of the present invention will now be described, by way of example with reference to the accompanying drawings in which.
Figure 1 shows a first stage in the production of an integrated circuit device or small electronic device incorporating a narrow feature, Figure 2 shows second and third stages in such production and Figure 3 shows fourth and fifth stages in such production.
Referring now to figure 1 of the drawing the production technique consists of first printing onto a wafer 1 the desired features, oversized, 2, in a thin metal masking layer 3 which is deposited on a planarising layer of polymer 4. The oversized features are compatably within the capability of the printing machine.
With reference to figure 2 the polymer 4 is oxygen plasma overetched so undercutting the metal mask 3 to produce the desired feature width 5. A sputtered coat of a second masking metal 6 then replicates the body of the remaining polymer 4.
With reference to figure 3 the undercut condition allows the float off removal of all traces of earlier steps using an acidic liquid. The second metal mask 6 carries the narrow features 5a as windows which can be replicated for example as the emitter contact windows 7 of a bipolar circuit in a silica layer.
The rate of diminuition of the polymer features in the oxygen plasma step approaches a near linear reproducible level and a precise optical measurement of the feature size 2 in the first masking layer may be used to tailor the required etch time to adequately control the final size 5a.
The process is extremely good for feature width reductions of 0.7 to 1.5 Mm and offers considerable economy in production compared to an electron beam patterning technology.

Claims (4)

Claims
1. An integrated circuit or similar small electronic device including a narrow feature, in which the narrow feature is produced by printing an oversized version of the narrow feature on an intermediate layer situated on top of the material in which the narrow feature is required, said oversize version being in a substance which is not etched by a subsequent etching process which is used to undercut the oversized feature thus producing a narrow feature whose width depends on the amount of etching.
2. An integrated circuit or similar small electronic device as claimed in claim 1 in which following the subsequent etching process a sputtered coat of metal is applied to the surface remaining, and in which the remaining portion of the intermediate layer is removed.
3. An integrated circuit or similar small electronic device including a narrow feature substantially as described with reference to the accompany drawings.
4. A method of producing an integrated circuit or similar device including a narrow feature substantially as described with reference to the accompanying drawings.
GB08326620A 1982-10-06 1983-10-05 Producing narrow features in electrical devices Expired GB2127751B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB08326620A GB2127751B (en) 1982-10-06 1983-10-05 Producing narrow features in electrical devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8228615 1982-10-06
GB08326620A GB2127751B (en) 1982-10-06 1983-10-05 Producing narrow features in electrical devices

Publications (3)

Publication Number Publication Date
GB8326620D0 GB8326620D0 (en) 1983-11-09
GB2127751A true GB2127751A (en) 1984-04-18
GB2127751B GB2127751B (en) 1986-04-23

Family

ID=26284056

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08326620A Expired GB2127751B (en) 1982-10-06 1983-10-05 Producing narrow features in electrical devices

Country Status (1)

Country Link
GB (1) GB2127751B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4236609A1 (en) * 1992-10-29 1994-05-05 Siemens Ag Method for forming a structure in the surface of a substrate - with an auxiliary structure laterally bounding an initial masking structure, followed by selective removal of masking structure using the auxiliary structure as an etching mask
EP1906229A2 (en) 2006-01-20 2008-04-02 Palo Alto Research Center Incorporated Process for forming a feature by undercutting a printed mask
US7749916B2 (en) 2006-01-20 2010-07-06 Palo Alto Research Center Incorporated Additive printed mask process and structures produced thereby

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1154015A (en) * 1966-08-22 1969-06-04 Photo Engravers Res Inst Inc Etching of Printed Circuit Components
GB1255039A (en) * 1968-03-01 1971-11-24 Ibm Improvements relating to the manufacture of semiconductor devices
GB1261651A (en) * 1968-03-01 1972-01-26 Ibm Method of making semiconductor devices
GB1510293A (en) * 1975-08-08 1978-05-10 Selenia Ind Elettroniche Manufacture of semiconductor devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1154015A (en) * 1966-08-22 1969-06-04 Photo Engravers Res Inst Inc Etching of Printed Circuit Components
GB1255039A (en) * 1968-03-01 1971-11-24 Ibm Improvements relating to the manufacture of semiconductor devices
GB1261651A (en) * 1968-03-01 1972-01-26 Ibm Method of making semiconductor devices
GB1510293A (en) * 1975-08-08 1978-05-10 Selenia Ind Elettroniche Manufacture of semiconductor devices

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4236609A1 (en) * 1992-10-29 1994-05-05 Siemens Ag Method for forming a structure in the surface of a substrate - with an auxiliary structure laterally bounding an initial masking structure, followed by selective removal of masking structure using the auxiliary structure as an etching mask
EP1906229A2 (en) 2006-01-20 2008-04-02 Palo Alto Research Center Incorporated Process for forming a feature by undercutting a printed mask
EP1906229A3 (en) * 2006-01-20 2008-04-23 Palo Alto Research Center Incorporated Process for forming a feature by undercutting a printed mask
US7498119B2 (en) 2006-01-20 2009-03-03 Palo Alto Research Center Incorporated Process for forming a feature by undercutting a printed mask
US7749916B2 (en) 2006-01-20 2010-07-06 Palo Alto Research Center Incorporated Additive printed mask process and structures produced thereby

Also Published As

Publication number Publication date
GB2127751B (en) 1986-04-23
GB8326620D0 (en) 1983-11-09

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PCNP Patent ceased through non-payment of renewal fee