GB1261651A - Method of making semiconductor devices - Google Patents

Method of making semiconductor devices

Info

Publication number
GB1261651A
GB1261651A GB01127/69A GB1112769A GB1261651A GB 1261651 A GB1261651 A GB 1261651A GB 01127/69 A GB01127/69 A GB 01127/69A GB 1112769 A GB1112769 A GB 1112769A GB 1261651 A GB1261651 A GB 1261651A
Authority
GB
United Kingdom
Prior art keywords
layer
gold
deposited
chromium
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB01127/69A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1261651A publication Critical patent/GB1261651A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H01L29/8122—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

1,261,651. Etching. INTERNATIONAL BUSINESS MACHINES CORP. 3 March, 1969 [1 March, 1968], No. 11127/69. Heading B6J. In a method of making semi-conductor devices, a first material is deposited on the surface of a. semi-conductor body to leave selected areas of the surface uncovered, a layer of a second material is deposited over the body which is then subjected to an etchant which penetrates the layer to dissolve underlying first material and subsequently any of the second material previously supported by the first material is removed. In a first embodiment, Figs. 1A-5A, a silicon substrate 1 bearing N- conductivity silicon layer 2 and a. silicon oxide layer 3 is etched at 5 in an atmosphere of hydrogen or argon. Concurrently with etching, N+ silicon is deposited. Ohmic contacts 7 are formed. by vapour deposition of gold/antimony and the protruding oxide edges removed by etching, ultrasonically or by wiping. The areas not covered: by silicon oxide are electrolytically coated with a nickel mask 10. The central silicon oxide bridge is then removed by etching through a. photo-resist with buffered hydrofluoric acid. A. layer of gold/chromium, G, is then deposited and the photoresist removed. The nickel mask 10 is then etched away with nitric acid. This acid also removes areas of nickel underlying areas of gold/chromium deposited therein in the step of forming area G. Finally all gold/chromium except at G is removed by wiping. In a second embodiment, Figs. 6-10, there is formed, on the surface of an N- silicon insert 24 in silicon dioxide layer 21, a layer 25 of gold/ antimony.. Part of, layer 21 is removed by etching, Fig. 7, and a. nickel layer 26 is deposited. A further portion of the silicon dioxide layer 21' is then removed by etching and the entire surface subsequently coated with gold/ chromium layer 22. Nickel layer 26 is then etched through the gold/chromium layer using nitric acid. The gold/chromium layer at 27. is then wiped off. The remaining gold/chromium layer 22 may then be electrolytically reinforced and a layer 23 of silicon dioxide deposited by cathode sputtering. Drain electrode 25<1> is then formed over the layer 23.
GB01127/69A 1968-03-01 1969-03-03 Method of making semiconductor devices Expired GB1261651A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH313168A CH471242A (en) 1968-03-01 1968-03-01 Method for the selective masking of surfaces to be processed

Publications (1)

Publication Number Publication Date
GB1261651A true GB1261651A (en) 1972-01-26

Family

ID=4249277

Family Applications (1)

Application Number Title Priority Date Filing Date
GB01127/69A Expired GB1261651A (en) 1968-03-01 1969-03-03 Method of making semiconductor devices

Country Status (5)

Country Link
JP (1) JPS4939550B1 (en)
CH (1) CH471242A (en)
DE (1) DE1909290A1 (en)
FR (1) FR1600775A (en)
GB (1) GB1261651A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2127751A (en) * 1982-10-06 1984-04-18 Plessey Co Plc Producing narrow features in electrical devices
CN116936687A (en) * 2023-09-18 2023-10-24 金阳(泉州)新能源科技有限公司 Combined passivation back contact battery and post-texturing method for removing undercut residual mask layer

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH484517A (en) * 1968-06-28 1970-01-15 Ibm Method for applying a substance to a limited surface area of a semiconductor
FR2104704B1 (en) * 1970-08-07 1973-11-23 Thomson Csf

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2127751A (en) * 1982-10-06 1984-04-18 Plessey Co Plc Producing narrow features in electrical devices
CN116936687A (en) * 2023-09-18 2023-10-24 金阳(泉州)新能源科技有限公司 Combined passivation back contact battery and post-texturing method for removing undercut residual mask layer
CN116936687B (en) * 2023-09-18 2023-12-15 金阳(泉州)新能源科技有限公司 Combined passivation back contact battery and post-texturing method for removing undercut residual mask layer

Also Published As

Publication number Publication date
DE1909290A1 (en) 1969-09-25
JPS4939550B1 (en) 1974-10-26
FR1600775A (en) 1970-07-27
CH471242A (en) 1969-04-15

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