DE1909290A1 - Method for selective masking, in particular for the production of semiconductor components of small dimensions - Google Patents

Description

IBM Germany Internationale Büro-MasMnen Gesellschaft mbH 1 90 9

Böblingen, February 24, 1969 si-ha

Applicant: International Business Machines

Corporation, Armonk, N.Y.10

Official file number: New registration

File number d. Applicant: Docket SZ 9-68-002

Method for selective masking, in particular for the production of Small size semiconductor components

In the technology of message processing, there is an interest in ever higher working speeds and thus higher Operating frequencies or pulse speeds of the devices. This interest leads to attempts, to processing These signals produce semiconductor elements that have particularly small inductances, capacitances and carrier transit times. That means, among other things. that certain geometric dimensions of the elements, such as. B. the channel length in field effect transistors, must be kept as small as possible.

SZ 9-68-002

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There are various limits to the endeavor to produce particularly small semiconductor elements. In planar technology, which is widely used today, in which a large number of similar elements or similar circuits are produced on a single substrate plate made of semiconductor material, masking methods are largely used to control the processes. For example, the semiconductor surface is covered with an insulating layer, such as semiconductor oxide, on which a light-sensitive lacquer is then applied, which has the property of being detachable in exposed areas in a subsequent process step and of continuing to adhere to unexposed areas or vice versa. In further process steps such as etching, diffusion, cathode sputtering, vacuum vapor deposition, galvanic application, etc., those areas of the substrate where the photoresist has been removed are processed. However, the optical imaging of fine patterns is limited by the occurrence of diffraction fringes at narrow slits. Even with the mask projection, high demands are placed on the flatness of the surfaces «in order to avoid blurring.

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For the production of semi-conductor elements in the a number of procedural steps are generally applied. and these often require repeated use of the ■ Photo masking process. For exact compliance with the geometric Dimensions, it is necessary that the successive masks with great accuracy in mutual Cover to be brought. With the desired size of the elements, this requirement is difficult to meet.

The procedure described below can be used to

Manufacture ladder elements that are particularly small geometric Have dimensions.

Another advantage of the method is that the necessary masking operations have low demands on the Alignment accuracy of the masks are to be provided.

The method described below therefore also has the advantage, particularly small and nevertheless inexpensive semiconductor elements, or produce integrated circuits see below.

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In the method according to the invention, a masking layer made of a first material is applied selectively to the material that is not to be processed Divide, applied to a surface. The masking layer is then covered by a thin layer of a second material resolved through, whereupon the second layer on the selectively masked surface parts can be removed in a simple manner.

In a special and preferred embodiment that can Method for the selective masking of surface parts of a semiconductor substrate are used. To cover Surfaces of a certain texture can be chosen a material and a precipitation method, which is a covering only effects these areas. The entire surface of the substrate is then covered with a thin layer of a second material, and the first material is replaced by the second dissolved through, whereby the layer of the second material is easily removable on the surfaces of a certain texture.

In a further embodiment of the method, metallic nickel can be used on the surface parts of the semiconductor substrate are deposited galvanically, which are electrically conductive. The substrate surface is then thinned with another Layer covered, which is now made removable by dissolving the nickel at the places previously covered with nickel.

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SZ 9-68-002

The method according to the invention will be explained in detail below with reference to the drawings. The drawings that the. show examples dealt with in the text;

Fig. 1 A and B in cross section and elevation, respectively. . a silicon substrate plate in "whose

Oxide cover windows have been etched;

Fig. 2 is a cross section through a window in

which the SiO was undercut;

Fig. 3 A and B the epitaxial precipitation of

N silicon in the window and under the

Undercut

Fig. 4 A and B the applied ohmic contacts,

as well as the Ni masking;

Figures 5 A and B show the completed Schottky barrier field. · Effect drainage.

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BATH ORIGINAL

Fig. 6 illustrates the first step of a further

Application example of the process, which is carried out on • another field effect transistor is set out;

Fig. 7 'represents a further method step, the

Nickel masking, the second example;

Fig. 8. shows the deposition of the second, the nickel

covering layer;

Fig. 9 illustrates the effect of removing the

Mask;

10 finally shows in a perspective view

the completed transistor. .

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The ancestor according to the invention »to ^ l'nujn i / n are individually described, with the production of a silicon field Effect transistor with Schottky barrier should serve as an example.

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The transistor to be manufactured is to have a high operational frequency

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• To achieve the frequency, have particularly small distances between the sources and the drainage electrode and, in particular, the control electrode should be designed to be particularly narrow. As already noted in the introduction, the previous technology sets certain limits here, for example the often used photo masking methods due to their limited resolution, because λ, do not allow the creation of particularly fine lines.

The starting material for the method should be the high-resistance, monocrystalline substrate plate 1, FIG. 1A made of silicon. The substrate plate is first by a known method with the weakly n-conducting layer 2 of about ₁ O 1 - provided to a thickness of 1, which later as the channel of the field - 0,2.Ohm cm and 0.5

Effect transistor should serve.

In a first process step, the substrate is coated with the oxide layer 3 of 0.2-0.5 µm thickness, which is known in the art Way e.g. in a Waeserdampfatmoaphäre at 950 C within from 30-60min. will be produced. It has proven to be advantageous, in a further step, the SiO. in an argon or acid

ο to stabilize the substance atmosphere for 10-20 minutes at 950 C, resp. to dry. However, this stabilization is not absolutely necessary and can also be omitted.

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In the next process step, the SiO in well-known

ia

White, e.g. with the help of a photo mask, two windows of e.g.

20 χ 250 µm etched in using buffered hydrofluoric acid, which will later accommodate the source and drainage electrodes. The window. 4 'are in Fig. IA and B in plan view, reep. cross-section shown. Their mutual distance should be as small as possible, B.B. 3 um in order to get by with only one SiO_ undercut.

The SiO layer is formed in a further process step

ζ »

5 - 10 minutes in the range between 950 and 1000 C in one

Hydrogen or argon atmosphere underetched laterally. It has been shown that in an atmosphere the gases mentioned are a. Removal of silicon dioxide and silicon takes place preferably in places where the oxide is in contact with silicon. One of the forms that arise in the process, which are of particular interest here, are shown in FIG. A removal 5 of the Oxide at the edge of the Si window occurs at high temperatures on. The dashed line in FIG. 2 indicates that in the surface area of the oxide no noticeable erosion has taken place. Εε thus arise in a ring that protrudes around the window 4 of the oxide layer Oxide edges 8.

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The effect of the preferred silicon and silicon dioxide etching on the edge of exposed Si windows has already been dealt with in the specialist literature, but without establishing the masking possibilities (jj

opportunity. It is known, for example, all of the often undesirable secondary t®

co ares in selective Si epitaxy and is based on the following q chemical reactions

SiO, + H, - »> SiO + H_O

Si + H-O- ^ SiO + H,

Also the direct reaction

SiO + Si ** 2SiO

cannot be ruled out completely. The stabilization (drying) dee oxide on the surface and decreased reactivity at low temperatures and increased Si - SiO distance are the presumptive prerequisites for a defined Undercut without noticeably enlarging the window. This effect is used usefully in the present case. How yourself has shown, the depth of the lateral undercut can be controlled quite well. An undercut depth of 1 µm is achieved in about 5 minutes, reached a depth of 4 µm in about 20 minutes. The undercutting of the oxide is advantageous in an epitaxy reactor at temperature

ο
doors between 950 and 1000 C. The erosion of the n-Si layer remains so small that it is insignificant for the construction of semiconductor elements, provided that the Si area exposed in the window is sufficiently large. At asu high temperatures, for example

carried. 909839/1432

above 1150 C, the oxide layer is completely removed.

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In the same process with the etching, which, as I said, can take place in flowing hydrogen or argon gas

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epitaxially, for example, η -conductive silicon can be applied. By adding Areen hydrogen ,, AsH- a thin layer is created, which should have a conductivity of about 0.01 Ohm. These highly conductive silicon layer serves _c series resistors between source electrode respectively runoff and reduce control electrode largely. The epitaxial application of n * silicon can be seen in FIG. 3. It is advantageous to break off the epitaxy before the end of the etching so that, as can be seen from FIG. 3, a small area 6 of weakly conductive η-silicon remains open under the protruding oxide layer. ^ This avoids breakthroughs between the control electrode and the other electrodes.

In a further method step _7, ohmic contacts 7 are deposited as terminals for the source and drain region on the surfaces within the window in the SiO. This is advantageously done by vacuum evaporation and alloying of a suitable material such as gold-antimony. When these contacts are vacuum-deposited, the overhanging oxide layer serves as a mask, and no electrode metal is deposited under the same.

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In a further process step, the protruding edge of the SiO_ layer is removed. This can be done by simply wiping the substrate surface with a cotton ball or the like, or by treating the substrate in a liquid-filled vessel with ultrasound, the brittle oxide layer breaking off. However, SiO ₇ etching can also occur

to

be undertaken, which only goes so far, the »just the protruding part 8 of the layer 3 is removed. The electrodes S and D for the source and drainage zone are now attached to the substrate. The narrow strip on which the control electrode G is to be attached is still with SiO_ covered; the separation distances between the electrodes are ·. formed by the oxide-free silicon surface 6.

In the following, the attachment of the control electrode G, which in this example should be a Schottky barrier electrode, set out. First, the separation distances are determined using a

Nickel marking 8 covered. This is done on all of SiO.

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free areas of the substrate nickel in a thickness of approx. 1000 AU electroplated. During electroplating, metallic nickel strikes the SiO. As is well known, covered areas are not low.

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The next step is a second photo mask produced, the now about Iu wide SiO, web between the two earlier etched windows ireiläeet in the oxide layer.

That is exactly the point to which the control electrode G starts.

should be brought. It should be noted that applying f \ j

this photomask is completely uncritical, as it only depends on it- ° comes that the mentioned bridge is left free. Whether the nickel-plated surfaces inside the old windows are covered oind or left bare does not matter, since basically this mask only serves to identify different transistors that are produced on the same substrate at the same time. differentiate from each other.

Now the contact surface for the control electrode, that is the unchanged surface of the substrate with the overlying n-layer 2 for the channel, by an oxide etching in buffered Hydrofluoric acid exposed. The metallic nickel 8, the outside the photomask covers the remaining parts of the Traneistore is not affected by this etching.

In a further process step, the Schottky barrier contact is then applied. For this purpose, as already known, chrome-gold or another suitable contact material is applied, but this is not alloyed into the silicon. Aet photoresist is then removed and excess chrome-gold that had deposited on the paint is wiped off at the same time;

90983 9 / U3 2

In a further process step, the metallic nickel, which is now the source and drainage zone, as well as the area between Source and drain electrode and control electrode covered, etched away. For this purpose, a caustic agent, e.g. ENT, is selected that only Attacks nickel metal, but does not affect the chrome-gold layers for the electrode connections. Now is the last step in the process the nickel surface 8 is covered with chrome gold which has been applied in order to form the control electrode G. Ee it has been shown that the etchant passes through this layer acts on the nickel because the layers are obviously not pore-free. After all, the chrome gold remains dee despite being etched away Nickel lies and must be removed extira, preferably wiped off.

In a last method coulter ride the connections for the electrodes are, as already known, galvanically reinforced, so that they are bonded or later some other way can be connected to lines .. The very narrow control electrode G is vorteilhafter- ι

wise provided with a pad 9 that allows the Connection wire easy to solder or bond. Depending on the size of the transistor, ea may be necessary, as well as the source S and the drain D to be provided with bolts connecting surfaces. The free Areas of the transistor are paseivated e.g. by cathode sputtering of SiO_ or another known method.

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In the following, the above is already intended using the example of a combined Oxide and nickel masking, on another Embodiment will be explained again briefly. This example also has a Schottky barrier field effect transistor

which, however, has a different structure. - CD

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another and possibly particularly cheap ax, the same Making transistor will be described.

The starting material is the highly conductive n '* ~ Si substrate plate 20 of the Fig. 6. This plate is first in a known manner with the relative thick SiO layer Zl coated. In this layer a

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Slot introduced, e.g. epitaxially with the n-silicon 24 is filled, which will later form the channel of the transistor. The metallization 25, e.g. from alloyed gold-antimony, which later serves as a connection for the drainage electrode.

The next step is part of the SiO layer 21 that is so thick is removed than it corresponds to the need for insulation between the control and drainage electrode, e.g. by etching. That The part of the channel 24 that protrudes thereafter, including the contact layer 2 5, is now, for example, electroplated with a metallic nickel layer 26 proven. Since nickel is only deposited on the Si surface and on the metallized surface 25, the oxide layer remains uncovered.

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In a further step, part of the SiO layer is removed again, so that the remaining oxide layer in turn has the thickness that corresponds to the need for insulation between the source and control electrode. The entire surface is now covered with a thin deposit of chrome-gold 22. The protruding end of the channel 24 with the already applied ohmic contact 25 and the nickel coating 26 is also covered by the layer 27. Ä

In the subsequent nickel etching, in which the etchant, such as already described in the above example, works through the chrome-gold layer, the nickel layer 26 is dissolved, whereupon the excess chrome-gold 27 can be wiped off. The chrome-gold layer 22 can now be electroplated be reinforced. On the exposed si of the canal

there is no precipitation, as this occurs in a short j

Time has passivated by the formation of a thin oxide layer. The end of the channel 24 with the electrode 25 is now exposed, and the transistor itself is now ready to use. It should be noted that no masking is required for manufacture was necessary, which would have required a difficult mask adjustment.

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The exposed control electrode layer 22 now becomes advantageous covered with SiO, e.g. by cathode sputtering

La

can be done. If this also covered the drainage electrode 25, this can be done by removing material, e.g. lapping, or by etching with the help of a photo mask be exposed. -.

The material used for the masking process described, in the two examples described, has nickel have the following properties: It must be oxide-free silicon, resp. Cover metal surfaces completely and without defects. It must Adhere sufficiently firmly to the base at least up to a certain thickness, and further treatments of the substrate, such as e.g. resist oxide etching, heating, cooling, etc. Ultimately, its removal, for example by selective Etching, by ultrasound treatment or by layer reinforcement, whereby peeling becomes possible, can be done easily and free of residue. Metallic nickel, deposited from an alkaline bath meets these requirements. However, other metallic or non-metallic materials are possible conceivable that relate to surfaces that have certain properties, selectively let down.

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Claims (6)

Claims ζ 1. ) A method for the selective masking of surfaces to be machined, in particular for the production of semiconductor components of small dimensions, characterized in that a masking layer of a first material is selectively applied to the non-machined parts of the surface and later by an overlaid, thin layer of a second material is dissolved through, in such a way that the second layer on the selectively masked surface parts can then be removed in a simple manner. 2. The method according to claim 1, for the selective masking of surface parts of a semiconductor substrate, characterized in that that a material and a precipitation method are selected to cover surfaces of a certain nature, which only covers these areas; that then the entire surface with a thin layer of a second material is covered, and that the first material is then dissolved through the second, whereby the layer of the second material is easily removable on the surfaces of a certain texture. 3. The method according to claim 2, characterized in that metallic nickel on conductive surfaces of the semiconductor substrate is applied galvanically, and that the substrate surface is then covered with a further thin layer that is attached to the previously areas covered with nickel are made removable by dissolving the nickel. 4. The method according to claim 3, characterized in that the layer covering the nickel consists essentially of "gold. sz 9-68-002 909 8 39 / Ula 5. The method according to claim 4, characterized in that that the gold layer has additions of chromium or antimony or both. 6. The method according to claim 4, characterized in that the nickel layer through the thin gold layer is dissolved in nitric acid. 909839/1412 Blank page