CH471242A - Method for the selective masking of surfaces to be processed - Google Patents

Method for the selective masking of surfaces to be processed

Info

Publication number
CH471242A
CH471242A CH313168A CH313168A CH471242A CH 471242 A CH471242 A CH 471242A CH 313168 A CH313168 A CH 313168A CH 313168 A CH313168 A CH 313168A CH 471242 A CH471242 A CH 471242A
Authority
CH
Switzerland
Prior art keywords
processed
selective masking
masking
selective
Prior art date
Application number
CH313168A
Other languages
German (de)
Inventor
Mohr Theodor
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Priority to CH313168A priority Critical patent/CH471242A/en
Priority to FR1600775D priority patent/FR1600775A/fr
Priority to JP44012675A priority patent/JPS4939550B1/ja
Priority to DE19691909290 priority patent/DE1909290A1/en
Priority to GB01127/69A priority patent/GB1261651A/en
Publication of CH471242A publication Critical patent/CH471242A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • H10D30/871—Vertical FETs having Schottky gate electrodes 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
CH313168A 1968-03-01 1968-03-01 Method for the selective masking of surfaces to be processed CH471242A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CH313168A CH471242A (en) 1968-03-01 1968-03-01 Method for the selective masking of surfaces to be processed
FR1600775D FR1600775A (en) 1968-03-01 1968-12-30
JP44012675A JPS4939550B1 (en) 1968-03-01 1969-02-21
DE19691909290 DE1909290A1 (en) 1968-03-01 1969-02-25 Method for selective masking, in particular for the production of semiconductor components of small dimensions
GB01127/69A GB1261651A (en) 1968-03-01 1969-03-03 Method of making semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH313168A CH471242A (en) 1968-03-01 1968-03-01 Method for the selective masking of surfaces to be processed

Publications (1)

Publication Number Publication Date
CH471242A true CH471242A (en) 1969-04-15

Family

ID=4249277

Family Applications (1)

Application Number Title Priority Date Filing Date
CH313168A CH471242A (en) 1968-03-01 1968-03-01 Method for the selective masking of surfaces to be processed

Country Status (5)

Country Link
JP (1) JPS4939550B1 (en)
CH (1) CH471242A (en)
DE (1) DE1909290A1 (en)
FR (1) FR1600775A (en)
GB (1) GB1261651A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2012004A1 (en) * 1968-06-28 1970-03-13 Ibm
FR2104704A1 (en) * 1970-08-07 1972-04-21 Thomson Csf

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2127751B (en) * 1982-10-06 1986-04-23 Plessey Co Plc Producing narrow features in electrical devices
CN116936687B (en) * 2023-09-18 2023-12-15 金阳(泉州)新能源科技有限公司 Post-texturing method for combined passivation of back contact cells and removal of undercut residual mask layer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2012004A1 (en) * 1968-06-28 1970-03-13 Ibm
FR2012003A1 (en) * 1968-06-28 1970-03-13 Ibm
FR2104704A1 (en) * 1970-08-07 1972-04-21 Thomson Csf

Also Published As

Publication number Publication date
JPS4939550B1 (en) 1974-10-26
GB1261651A (en) 1972-01-26
FR1600775A (en) 1970-07-27
DE1909290A1 (en) 1969-09-25

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Legal Events

Date Code Title Description
PL Patent ceased