GB2118007A - Adjustable coring circuit - Google Patents

Abstract

Signals to be cored are applied to the inputs of a linear signal amplifier (13), and of a multistage limiting amplifier (15) having cascaded input and output amplifying stages. A cored version of the signals, corresponding to the difference between a linearly translated version of the signals and a doubly clipped version thereof, is developed by a signal combiner (17) responsive to the outputs of both amplifiers. A variable coring level control voltage (21) controls the distribution of gain between the input and output amplifying stages, substantially without disturbing the overall gain of the limiting amplifier, which is set to match the overall gain of the linear amplifier. In an illustrative embodiment, the signals which are adjustably cored are horizontal peaking signals derived from the received luminance signal in a color television receiver. An automatic peaking control system associated with output of the adjustable coring circuit opposes changes in peaking level that might otherwise accompany coring level adjustment. <IMAGE>

Description

SPECIFICATION Adjustable coring circuit The present invention relates generally to adjustable signal coring circuits.

Coring of a signal (i.e., removing a close-toaverage-axis "core" of the signal, by processing the signal with a translator exhibiting a transfer characteristic with a dead zone for close-to-axis signal excursions) is a known signal processing function, occasionally resorted to for noise reduction purposes, as explained, for example, in an article by J. P. Rossi, entitled "Digitai Techniques for Reducing Television Noise", appearing on pages 134-140 of the March, 1 978 issue of the SMPTE Journal. In certain uses of a coring circuit, a facility for adjusting the level of coring to be effected may be desired. The facility may permit manual adjustment of the coring level (as shown, for example, in an article by R. H.McMann, et al., entitled "Improved Signal Processing Techniques for Colour Television Broadcasting", appearing on pages 221-228 of the March 1968 issue of the SMPTE Journal), or may provide for a dynamic adjustment of coring level (as shown, for example, in U. S. Patent No.

4,167,749 -- Burrus, where a coring level is varied as a function of the level of noise detected as accompanying a video signal).

The present invention is concerned with the provision of a coring circuit of a type permitting coring level adjustment, but which avoids the need for capacitive elements in its structure, and is conveniently and efficiently realizable in integrated circuit form. In use of such a coring circuit, the minimum coring level extreme of the coring level adjustment may permit a finite residual coring level.

In accordance with the principles of the present invention, a signal to be cored is applied to the input of a linear signal translator and to the input of a non-linear signal translator, the latter comprising a multistage limiting amplifier for developing a limited version of the signals, and exhibiting an overall gain substantially equal to the gain exhibited by the linear signal translator. The limiting amplifier includes first and second signal amplifying stages coupled in cascade for signal amplification purposes. A signal combiner, responsive to outputs of the two signal translators, develops a cored version of the signals corresponding to the difference between a linearly translated version of the signals and a limited version of the signals.To achieve adjustment of the coring level, means are coupled to the cascaded amplifying stages of the limiting amplifier to alter the distribution of gain therebetween substantially without disturbance of the overall gain of the limiting amplifier.

In accordance with an illustrative embodiment of the present invention, the cascaded amplifying stages of the limiting amplifier comprise respective differential amplifiers, each deriving its operating current from the collector electrode of a respective current source transistor. The baseemitter paths of the respective current source transistors are connected in series across a common source of bias. Variation of a variable DC impedance connected in shunt with the baseemitter path of one of the current source transistors effects the desired coring level control.

Illustratively, the variable DC impedance comprises the collector-emitter path of a first control transistor having an adjustably biased base-emitter junction.

In an illustrative use of the present invention, the signal which is subject to adjustable coring is a peaking signal derived from the luminance component of a television signal for use in enhancement of horizontal detail in an image reproduction. In such use of the invention, the adjustably cored peaking signal is desirably thereafter subject to the action of a closed loop automatic peaking control system so as to substantially prevent the adjustments of coring level from having undesired effects on the level of peaking attained.

In accordance with a further modification of the present invention, the above-described coring system can permit extinction of coring action to be automatically obtained at the minimum coring level extreme of the coring level control range.

In this modification, the coring level control system utilizes a second control transistor in addition to the above-described first control transistor, with the respective control transistors being of opposite conductivity types. The emitter electrode of the second control transistor is connected to the base electrode of one of the current source transistors of the limiting amplifier and the emitter-collector path of the second control transistor is shunted across the series combination of the base-emitter paths of the two current source transistors. The base electrode of the second control transistor is rendered responsive to the same coring level control voltage that is used to adjustably bias the first control transistor. Over a wide portion of the coring level control range, the base-emitter junction of the second control transistor is reverse biased.Under such circumstances, the second control transistor is cut off, and operation of the adjustable coring is unaffected thereby. In the vicinity of the minimum coring level extreme of the coring level control range, however, the baseemitter path of the second control transistor becomes forward biased. Strong conduction by the second control transistor when the minimum coring level extreme of the coring level control range is reached produces a disabling of the limiting amplifier, permitting extinction of the coring action.

In the drawing: FIGURE 1 illustrates, by block diagram representation, a coring circuit embodying the principles of the present invention; FIGURE 2 illustrates, partially schematically and partially by block representation, an illustrative implementation of the coring circuit of FIGURE 1 for achievement of adjustable coring of a peaking signal in a television receiver; and FIGURE 3 illustrates, by block diagram representation, an automatic peaking control system with which the apparatus of FIGURE 2 may desirably be associated.

In the system of FIGURE 1, signals from a signal source 11 are supplied to the inputs of a linear amplifier 1 3 and of a multistage limiting amplifier 15. The magnitude of the overall gain (+G1) provided by the multistage limiting amplifier 1 5 is equal to the magnitude of the gain (-G1) of the linear amplifier 13. The outputs of the respective amplifiers are in antiphasal relationship, with the linear amplifier 13, illustratively, providing a net phase inversion, whereas limiting amplifier 1 5 is non inverting.

The output of the linear amplifier 13 is a linearly translated version of the input signals, whereas limiting amplifier 1 5 serves as a non-linear signal translator providing a doubly clipped version of the input signals. Summing of the outputs of the respective amplifiers 13, 1 5 is carried out by a signal combiner 1 7 to form a cored version of the input signals for delivery to a signal utilization circuit 1 9. The waveform of the cored signals delivered to utilization circuit 19 corresponds to the waveform of the input signals less its central, close-to-axis "core", which has been removed by cancellation in the combiner 1 7.

The distribution of gain between cascaded stages of the multistage limiting amplifier 15 is subject to adjustment by a gain distribution control circuit 23, in response to a control voltage developed by a variable coring control voltage source 21, substantially without disturbance of the overall gain of limiting amplifier 1 5. A convenient technique for so changing the distribution of gain between cascaded stages of a multistage amplifier is disclosed, for example, in U.

S. patent application, entitled "Amplifier Incorporating Gain Distribution Control For Cascaded Amplifying Stages", Serial No. 363,896 filed on March 31, 1982 (RCA 76634, British Appin. No. 8308451 filed concurrently herewith).

As the distribution of gain between cascaded input and output stages of amplifier 1 5 is altered in response to a variation of the control voltage supplied by source 21, the relative magnitude of the core subject to removal in combiner 17 is changed. That is, the depth or level of coring of the input signals is adjusted in response to a variation of the coring control voltage. A gain distribution change that increases input stage gain results in a clipping by the output stage that is closer to the axis, and thus reduces the coring level. Conversely, a gain distribution change that decreases input stage gain increases the coring level.Maintenance of the overall gain amplifier 15 substantially constant in the face of the gain distribution changes, however, assures the matching relationship between portions of the waveforms of the inputs to combiner 1 7 that is required for accurate cancellation therein so as to produce coring at the selected level.

In FIGURE 2, an illustrative embodiment of the coring system of FIGURE 1 is shown in schematic detail, performing the function of adjustable coring of a horizontal peaking signal in a television receiver. In the FIGURE 2 embodiment, a differential amplifier 40 serves as the linear amplifier of the FIGURE 1 system, and differential amplifiers 50 and 60 serve as the cascaded input and output stages of the multistage limiting amplifier of the FIGURE 1 system.

To develop the peaking signal which is to be processed by circuitry embodying the principles of the present invention, the output of a luminance signal source 25 (e.g., in a colour television receiver use, constituted by the luminance signal output of the receiver's comb filter) in coupled via a resistor 27 to the input terminal (L) of a delay line 29. Illustratively, the delay line 29 is a wideband device exhibiting a linear phase characteristic over the frequency band occupied by the signals from source 25 (e.g., extending to 4.0 MHz.), and provides a signal delay of 140 nanoseconds. The input end of delay line 29 is terminated (e.g., through the aid of resistor 27) in an impedance substantially matching its characteristic impedance, whereas the output end of the delay line (at terminal L') is misterminated to obtain a reflective effect.The signals appearing at the respective ends of the delay line 29 are thus: (a) a once-delayed luminance signal at terminal L', and (b) the sum of an undelayed luminance signal and a twice-delayed luminance signal at terminal L. The difference between the respective signals at terminals L and L' corresponds to an appropriate horizontal peaking signal for addition to the luminance signal to enhance its horizontal detail (by effectively boosting luminance components in a frequency range from 1.75MHz.

to 5.25 MHz., db points, with a maximum boost at 3.5 MHz.).

Differential amplifier 40, accepting signals from terminals L and L' at its respective differential inputs, provides a linear amplification channel for such a peaking signal. Amplifier 40 includes a pair of NPN transistors 41,43 with interconnected emitter electrodes returned to a point of reference potential (e.g., ground) via the coilector-emitter path of an NPN current source transistor 45 in series with emitter resistor 46. The base electrode of transistor 45 is connected to the positive terminal (+1.2 V.) of a bias potential supply to establish a desired operating current for amplifier 40.

Signals from terminal L' are supplied to the base electrode of transistor 41 via the baseemitter path of an NPN emitter-follower transistor 34 and a series coupling resistor 36. The collector electrode of transistor 34 is directly connected to the positive terminal (+Vcc) of an operating potential supply, while the emitter electrode of transistor 34 is returned to ground via the collector-emitter path of a current source transistor 35 (having its base electrode connected to the +1.2 V. bias supply terminal) in series with emitter resistor 26. Signals from terminal L are supplied to the base electrode of transistor 43 via the base-emitter path of an NPN emitter-follower transistor 30 and a series coupling resistor 32.

The collector electrode of transistor 30 is directly connected to the +Vcc supply terminal, while the emitter electrode of transistor 30 is returned to ground via the collector-emitter path of a current source transistor 31 (having its base electrode connected to the + 1.2 V. bias supply terminal) in series with emitter resistor 28. While direct connections are illustrated between the respective terminals L, L' and the bases of emitter-follower transistors 30, 34, additional emitter-followers (not shown) may desirably be interposed in the respective connections to increase the impedances presented to the respective terminals.

A resistor 38 interconnects the base electrodes of transistors 41, 43, and cooperates with the coupling resistors 36, 32 to introduce a degree of attenuation of the input signals that ensures that the maximum signal difference between base potentials is accommodated within the linear signal handling range of amplifier 40. The respective collector electrodes of transistors 41 and 43 are linked to the positive terminal of an operating potential supply by respective loads (not shown) which are shared by the limiting amplifier's outputs. The respective collector currents of transistors 41 and 43 vary in accordance with oppositely phased versions of the peaking signals.

Differential amplifier 50, accepting signals from terminal L and L' at its respective differential inputs, serves as the input stage of a limiting amplifier providing a non-linear amplification channel for the peaking signal. Amplifier 50 includes a pair of NPN transistors 51, 53 with interconnected emitter electrodes returned to ground via the collector-emitter path of an NPN current source transistor 55. Signals from terminal L', appearing at the output of emitter-follower transistor 34, are supplied to the base electrode of transistor 51 via a series coupling resistor 37.

Signals from terminal L, appearing at the output of emitter-follower transistor 30, are supplied to the base electrode of transistor 53 via a series coupling resistor 33. A resistor 39 interconnects the base electrodes of transistors 51 and 53. The input signal attenuation provided by the network of resistors 37, 39, 33 is less than the attenuation provided by the linear amplifier network (36, 38, 32), and permits the maximum signal swing between bases to exceed the linear signal handling range of amplifier 50.

The collector electrodes of transistors 51 and 53 are individually connected by respective load resistors (57, 59) to the positive terminal (+4.0 V.) of an operating potential supply. Oppositely phased peaking signals (with maximum excursions clipped) appear across the respective load resistors 57 and 59.

Differential amplifier 60, serving as the output stage of the limiting amplifier and providing further clipping of the peaking signals, includes a pair of NPN transistors 61 and 63 with emitter electrodes connected to the collector electrode of a current source transistor 65. The emitter electrode of transistor 65 is returned to ground via the base-emitter path of current source transistor 55. The base electrode of transistor 61 is directly connected to the collector electrode of transistor 51 of the input stage, while the base electrode of transistor 63 is directly connected to the collector electrode of transistor 53 of the input stage.

The collector electrode of transistor 61 is directly connected to the collector electrode of transistor 41 of the linear amplifier so that the summed collector currents of transistors 41 and 61 form a cored peaking signal current (Ip'). The collector electrode of transistor 63 is directly connected to the collector electrode of transistor 43 of the linear amplifier so that the summed collector currents of transistors 43 and 63 form a cored peaking signal current Ip (an oppositely phased version of Ip').

A resistor 66 is connected between the positive terminal (+3.2 V) of a bias potential supply and the anode of a diode 67, the cathode of which is directly connected to the anode of a second diode 68. The cathode of diode 68 is directly connected to ground, so that the pair of diodes 67, 68 are forward biased by the bias potential supply. The anode of diode 67 is directly connected to the base electrode of current source transistor 65, so that the voltage appearing across the diode pair (67, 68) is applied across the serially disposed base-emitter paths of current source transistors 65, 55 to forward biase their base-emitter junctions.

The collector electrode of an additional NPN transistor 71 is directly connected to the base electrode of transistor 55. The emitter electrode of sstransistor 71 is directly connected to ground, placing the collector-emitter path of transistor 71 directly in shunt with the base-emitter path of the input stage's current source transistor 55.

A coring control voltage input terminal CC is connected to the base electrode of an NPN emitter-follower transistor 75 (having its collector electrode directly connected to the +Vcc supply terminal). The emitter electrode of transistor 75 is connected via resistor 73 to the base electrode of transistor 71, and to the anode of a diode 72. The cathode of diode 72 is directly connected to ground, placing diode 72 directly in shunt with the base-emitter path of transistor 71. A positive coring control voltage applied to terminal CC controls the biasing of transistor 71 to vary the conductance of its collector-emitter path and thereby adjust the level of coring attained in the output signal current Ip and Ip'.

A PNP control transistor 69 is disposed with its emitter electrode directly connected to the base electrode of current source transistor 65. The collector electrode of transistor 69 is returned directly to ground, placing the emitter-collector path of transistor 69 directly in shunt with the series combination of the base-emitter paths of the two current source transistors 65, 55. The base electrode of control transistor 69 is directly connected to the coring control voltage input terminal CC.

The coring control voltage source is illustratively shown in the drawing as a manually controlled potentiometer 21, with its adjustable tap directly connected to terminal CC, and with its fixed end terminals connected respectively to the positive terminal (+V) of a DC voltage source, and to the grounded negative terminal thereof.

Illustratively, the potential at the +V terminal is appreciably larger than the (2be) potential developed across the series combination of diodes 67, 68. Thus, the base-emitter junction of PNP transistor 69 remains reverse biased over a large portion of the tap adjustment range (when the control potential selected by the tap exceeds the 2Vbe potential). The variable coring control voltage may also be provided by a dynamic control source (as in the aforementioned Burrus patent, for example). Over the large portion of the adjustment range, the PNP control transistor 69 is cut off, and operation of the adjustable coring system is as set forth immediately below.

The base-emitter path of transistor 65 forms a voltage divider with the parallel combination of (a) the base-emitter path of transistor 55, and (b) the collector-emitter path of transistor 71, to effect a division of the bias voltage appearing across the series-connected diodes 67, 68, with the division ratio dependent upon the conductance of NPN control transistor 71. When the shunting impedance presented by transistor 71 decreases (due to an increase in the coring control voltage), the base-emitter voltage (Vbe) of current source transistor 55 decreases, accompanied by a complementary increase of the base-emitter voltage of current source transistor 65.When the shunting impedance presented by transistor 71 increases (due to a decrease in the coring control voltage), the Vbe of transistor 55 increases, accompanied by a complementary decrease of the Vbe of transistor 65.

The consequence of a variation of the coring control voltage is thus an introduction of complementary variations in the operating currents of differential amplifiers 50 and 60, and, hence, complementary variations of the respective gains of the two cascaded stages of the limiting amplifier. With variation of the DC impedance presented by transistor 71 having a negligible effect on the bias voltage appearing across diodes 67, 68, the overall gain of the limiting amplifier, proportional to the product of the magnitudes of the respective stage's operating current, remains substantially undisturbed as the distribution of gain between respective stages is varied. For accuracy of coring, this undisturbed magnitude of overall gain is set so that the gain of the respective non-linear and linear amplification channels are substantially identical.

A gain distribution change (caused by a decrease in coring control voltage) that elevates input stage (50) gain results in a clipping by the output stage (60) that is closer to the axis, and thus reduces the coring level. Conversely, a gain distribution change (caused by an increase in coring control voltage) that depresses input stage gain increases the coring level.

As the position of the adjustable tap approaches the grounded end terminal of potentiometer 21, however, the biasing of the base-emitter junction of the PNP control transistor 69 shifts to the forward direction, and conduction in the emitter-collector path of transistor 69 occurs. At the control range extreme that places the tap at ground potential, this conduction is sufficiently great as to result in cutoff of the current source transistors 65, 55, and consequent extinction of the coring of the horizontal peaking signals.

FIGURE 3 illustrates additional signal processing apparatus with which the peaking signal corer of FIGURE 2 may be desirably associated. In FIGURE 3, the (push-pull) cored peaking signal outputs (Ip and Ip') of the FIGURE 2 system are supplied as signal inputs to a gain controlled peaking signal amplifier 101. Amplifier 101 translates the cored peaking signals with a gain (or attenuation) determined by a control voltage applied to a peaking control terminal PC.

The push-pull outputs of amplifier 101 are summed with the push-pull outputs of a luminance signal amplifier 105, responsive to the delayed luminance signals at terminal L' (FIGURE 2), in a signal combiner 103 to form push-puil versions of a peaked luminance signal for application to a peaked luminance signal amplifier 107. Amplifier 107 converts the push-pull peaked luminance signal inputs to single-ended form at output terminal 0, from which terminal the peaked luminance signal may be delivered, for example, to a color receiver's matrix circuits for combination with respective color-difference signals.

The output of amplifier 107 is also applied to the input of a bandpass amplifier 109 for automatic peaking control purposes. Illustratively exhibiting a passband of approximately 1 MHz.

bandwidth centered about a frequency of approximately 2 MHz., amplifier 109 delivers the components of the peaked luminance signal falling within its passband to a peak detector 110, which develops a control voltage proportional to the amplitude of the delivered components. This control voltage is applied to terminal PC to control the magnitude of the peaking signals supplied to combiner 103 in a sense opposing changes in the amplitude of said delivered components.

Reference may be made to British Patent Appln.

2107552 corresponding to U.S. Patent application, Serial No. 310,139, filed October 9, 1 981 for a more detailed explanation of the operation of such an automatic peaking control system, and examples of advantageous circuitry for implementing the functions of the elements 101,103,105,107, 109 and 1 10 (as well as associating a manual peaking control therewith).

An advantage of associating the apparatus of FIGURE 3 with the adjustable coring system of FIGURE 2 resides in the substantial avoidance of any adverse effects on peaking level when the coring level is adjusted. To illustrate this point, consider, for example, that a coring control voltage change is made to increase the coring level for purposes of increased removal of noise components from the peaking signal outputs of the FIGURE 2 system. One accompanying consequence of such a greater core removal is a reduction of the amplitude of the retained peaking signal components in outputs Ip and Ip'. The automatic peaking control system of FIGURE 3, however, will tend to oppose any weakening of peaking effects that such amplitude reduction might otherwise cause by introducing a compensatory change in the gain of amplifier 101.

An illustrative set of values for circuit parameters of the FIGURE 2 system is, as follows: Resistors 26, 28 2 kilohms Resistor 27 680 ohms Resistors 32, 36 2.4 kilohms Resistors 33, 37 470 ohms Resistor 38 1000 ohms Resistor 39 4.7 kilohms Resistors 46, 57, 59 500 ohms Resistor 66 13.3 kilohms Resistor 73 25 kilohms Potential (+Vcc) 11.2 volts

Claims (13)

1. A system for providing an adjustable amount of coring of signals derived from a source said system comprising first signal translating means having an input coupled to said source, for linearly translating said signals; second signal translating means having an input coupled to said source, for non-linearly translating said signals; said second signal translating means comprising a multistage limiting amplifier for developing a limited version of said signals, said limiting amplifier including first and second signal amplifying stages coupled in cascade, and exhibiting an overall gain substantially equal to the gain exhibited by said first signal translating means; cored version developing means responsive to the outputs of said first and second signal translating means, for developing a cored version of said signals corresponding to the difference between a linearly translated version of said signals and a limited version of said signals; and gain distribution varying means coupled to said first and second signal amplifying stages, for selectively altering the distribution of gain between said first and second signal amplifying stages substantially without disturbance of said overall gain of said limiting amplifier.

2. A system in accordance with claim 1 wherein one of said signal translating means, to the exclusion of the other, subjects said signals to a net phase inversion, and wherein said cored signal developing means includes means for summing outputs of said first and second signal translating means.

3. A system in accordance with claim 1 or 2, wherein in that said source is a source of luminance signals, and the signals translated by said first and second signal translating means comprise peaking signals derived from said luminance signal source.

4. A system in accordance with claim 3, comprising: a gain controlled peaking signal amplifier responsive to the output of said cored version developing means means for combining the output of said gain controlled peaking signal amplifier with luminance signals derived from said source to form a peaked luminance signal output; and means responsive to said peaked luminance signal output, for controlling the gain of said peaking signal amplifier.

5. A system in accordance with claim 4 wherein said gain controlling means includes a frequency selective amplifier having an input coupled to receive said peaked luminance signal output, said frequency selective amplifier exhibiting a pass band encompassing a high frequency portion of the frequency spectrum occupied by said luminance signals; and a peak detector responsive to the output of said frequency selective amplifier for developing a gain control voltage.

6. A system as claimed in claim 1 wherein said source is a source of luminance signals in a television receiver; a delay line its input coupled to said source of luminance signals; said first signal translating means includes a linear signal translator comprising a first differential amplifier having a pair of inputs coupled to be responsive to signals appearing at the input of said delay line and to signals appearing at the output of said delay line, respectively; said second signal translating means includes a non-linear signal translator, comprising a limiting amplifier including second and third differential amplifiers coupled in cascade, said second differential amplifier having a pair of inputs coupled to be responsive to signals appearing at the input of said delay line and to signals appearing at the output of said delay line, respectively;; said gain distribution varying means is coupled to said second and third differential amplifiers, for simultaneously varying the gains of said second and third differential amplifiers in mutually opposite directions; the overall gain of said non linear signal translator being independent of the operation of said gain distribution varying means and substantially equal to the gain of said linear signal translator; said cored version developing means combines the outputs of said linear translator and said nonlinear signal translator to form a cored peaking signal, with the level of coring dependent upon the operation of said gain varying means.

7. A system in accordance with claim 6 comprising: a gain controlled peaking signal translator responsive to said cored peaking signal; means for combining the output of said gain controlled peaking signal translator with luminance signals derived from said source to form a peaked luminance signal; a frequency selective amplifier having an input responsive to said peaked luminance signal and exhibiting a pass band encompassing a high frequency region of the frequency band occupied by said luminance signal; and means responsive to the amplitude of an output of said frequency selective amplifier for controlling the gain of said peaking signal translator.

8. A system as claimed in claim 1, wherein: said cored version developing means includes a bias voltage source a first current source transistor having base, emitter and collector electrode, for supplying operating current to said input amplifying stage a second current source transistor having base, emitter and collector electrodes, for supplying operating current to said output amplifying stage the respective base-emitter paths of said first and second current source transistors being connected in series across said bias voltage source;; first and second control transistors, each having base, emitter and collector electrodes, said first and second control transistors being of mutually opposite conductivity types, the collector-emitter path of said first control transistor being connected in shunt with the baseemitter path of said first current source transistor the collector-emitter path of said second control transistor being connected in shunt with the series combination of the base-emitter paths of said first and second current source transistors; a source of variable DC voltage; and means for rendering the base electrodes of both said first and second control transistors responsive to said variable DC voltage.

9. A system in accordance with claim 8 wherein the polarity of said variable DC voltage is such as to effect variable forward biasing of the base-emitter junction of said first control transistor.

10. A system in accordance with claim 9 wherein the range of variation of said variable DC voltage is such that said second control transistor is maintained in a nonconducting state in response to values of said variable DC voltage over a major portion of said variation range.

11. A system in accordance with anyone of claims 8-10 wherein said current source transistors are of the same conductivity type NPN) as said first control transistor.

1 2. A system in accordance with claim 11 wherein each of said amplifying stages comprises a differential amplifier including a pair of transistors of the same conductivity type as said first control transistor, with interconnected emitter electrodes connected to the collector electrode of a respective one of said current source transistors.

13. A system for providing an adjustable amount of coring of signals and substantially as hereinbefore described with reference to Figure 1, or to Figures 1 and 2 or to Figures 1,2 and 3.