KR930004548Y1 - Rgb signal amplication circuit - Google Patents

Abstract

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Description

R, G, B signal amplification circuit

1 is a conventional R, G, B signal amplification circuit diagram.

2 is a R. G. B signal amplification circuit according to the present invention.

3 is a crosstalk generation waveform diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

1, 2, 3: R. G. B amplifier circuit 4: Bias circuit

11, 21, 31,: bias buffer

The present invention relates to a circuit for preventing crosstalk between three amplifying circuits for amplifying R, G, and B video signals. In particular, the present invention relates to a circuit for amplifying R, G, and B video signals in a color monitor of a PC. The present invention relates to R, G, and B signal amplification circuits suitable for preventing crosstalk between amplifiers.

In the conventional R, G, and B signal amplification circuits, as shown in FIG. 1, the R, G, and B signal inputs Rin, Gin, and Bin terminals are transistors Q1, Q4, and ( The collectors of the transistors Q1, Q4, and Q7 connected to the base of Q7, and the emitters are grounded through the ground capacitors R1, R3, and R5 are respectively transistors Q2, The bias output (V1), (V2) terminals connected to the emitters of Q3), (Q5, Q6) and (Q8, Q9) and bias-adjusted according to the variable resistor (V _R1 ) are respectively ground capacitor (C2), The bias output (V1), (V2) terminals of the bias circuit (4) connected to (C1) are connected to the bases of the transistors (Q2, Q5, Q8), (Q3, Q6, Q9), respectively. The collector connection points of the transistors Q3, Q6, and Q9 to which the resistors R2, R4, and R6 are connected are R, G, B outputs Rout, Gout, and Bout, respectively. R, G, and B signal amplifying circuits 1, 2, and 3 were respectively connected to the terminals.

Referring to the operation and problems of the conventional R, G, B signal amplification circuit configured as described above are as follows.

When the R signal input Rin is applied to the base of the transistor Q1, the emitters of the collectors of the transistor Q1 are commonly connected through the transistor Q1, and the transistors Q2 and Q3 act as differential amplifiers. According to the differential amplification, R output Rout appears at the collector side of transistor Q3.

In this case, the gain is determined by the emitter resistor Q1 of the transistor Q1 and the collector resistor R2 of the transistor Q3 (R2 / R1), and the automatic amplification transistors Q2 and Q3 have a bias circuit 4 at the base. Since the bias outputs V1 and V2 are applied, the bias applied according to the adjustment of the bias control variable resistor V _R1 is adjusted to adjust the gain R2 / R1 by the resistors R1 and R2. do.

Similarly, the G, B signals Gin and Bin are also amplified by the G. B signal amplifying circuits 2 and 3, respectively, and outputted to Gout and Bout. Here, the capacitors C1 and C2 are the differential amplifier transistors Q2 and Q3 and Q5 and Q6 of the amplification circuits 1, 2, and 3, respectively. Since the biases V1 and V2 applied to the bases of Q8 and Q9 are applied, the bias is commonly supplied so that crosstalk between the amplifying circuits 1, 2, and 3 is improved.

However, such conventional R, G, B amplifier circuits have a convenient advantage in that the gains of three amplification circuits (1), (2), and (3) are commonly adjusted. , (2), (3) Crosstalk between each other causes deterioration of amplification circuit characteristics. This phenomenon causes more serious problems in broadband amplifiers each equipped with three channels of R, G, and B amplification circuits. Can be.

In consideration of such a problem, the present invention buffers and applies bias applied to the differential amplification transistor, thereby devising a circuit to suppress crosstalk generated between the R, G, and B amplifier circuits. With reference to the following in detail.

2 is an R, G, B amplification circuit diagram according to the present invention, as shown in the transistors (Q2, Q3), which is applied to the bias circuit (4) bias output (V1, V2) to each of the base to automatically amplify, Transistors (Q1), (Q4), and a collector connected to each common emitter (Q5, Q6) and (Q8, Q9) and ground resistors (R1), (R3), and (R5) respectively connected to the emitter. R, G, B signals (Rin), (Gin), (Bin) inputs are applied to the base of (Q7), respectively, to pull-up resistors (R2) and (R4). R, G, and B through the collector connection points of the output transistors Q3, Q6, and Q9 through the collector connection points of the transistors Q3, Q6, and Q9 connected to R6. , R, G, B (1), (2) for B output (Rout), (Gout), (Bout). (3), the emitters of the transistors Q11, Q13, Q21, Q23, Q31, Q33 applied to the bias output V1 and mace of the bias circuit 4 1), (2), and (3) are connected to the bases of the differential amplification transistors (Q2, Q3), (Q5, Q6) and (Q8, Q9), and the transistors (Q11), (Q21), and (Q31). The emitter of) is connected to the collector connection point of the current source transistors Q12, Q22, and Q32 to which the collector and the base are connected through resistors R11, R21, and R31, and the transistors Q13, ( The emitters of Q23) and Q33 are connected to the collectors of current source transistors Q14, Q24, and Q34, which are common bases with the current source transistors Q12, Q22, and Q32, respectively, respectively. 11), (21), and (31), and buffers the bias outputs (V1) and (V2) of the bias circuit (4) to differential amplification stages of the amplification circuits (1), (2), and (3). It was configured to apply a bias.

Referring to the operation and effects of the present invention configured in this way as follows.

Referring to the R signal Rin as an example, the R signal Rin is input to the base of the amplifying circuit 1 transistor Q1 and amplified through the transistor Q1 acting as a common emitter of the differential amplifier stage, and then the other. The amplified R output Rout can be obtained through the collector of the differential amplification transformer Q3 operating as a common base with the amplifying circuit.

At this time, the gain of the maximum gain R2 / R1 is obtained by the transistor Q1, and the gain of the transistor Q1 is adjusted by the base voltage difference between the two ends of the transistors Q2 and Q3 having the differential amplifier configuration.

This process is the same as in the prior art, and the G signal Gin and the B signal Bin are also amplified by the same action as the R signal Rin through the amplification circuits 2 and 3, respectively. , (Bout).

Here, when the video signal passes through the transistors Q3, Q6, and Q9 operating as a common base, crosstalk is generated by a signal fed back to the base by parasitic capacitors Cbc and Cbe of each transistor. To prevent this, the base bias is respectively bias buffer (11), (21). In this case, the signal is fed back by 31 to block the signal fed back by the buffer, thereby preventing other amplifier circuits from being affected.

That is, the bias outputs V1 and V2 of the bias circuit 4 are connected to the transistors Q11, Q13, Q21, Q23, Q31, Q33 of the bias buffers 11, 21, and 31, respectively. After supplying the buffer through the buffer amplifier, the common base bias of the differential amplifier stage is supplied, and the transistors Q11, Q13, Q21, Q23, and Q31. ), The base voltage is balanced at both ends through current source transistors (Q12, Q14), (Q22, Q24), and (Q32, Q34) which are common bases with (R31).

Accordingly, the crosstalk generated by the parasitic capacitors of the transistors Q3, Q6, and Q9 is fed back from the amplifying circuit on one side to the base of the other amplifying circuit, and thus the transistors Q13 and Q23 of each buffer. It prevents crosstalk because it blocks the signal from being fed back by Q33.

3 is a crosstalk waveform diagram according to the present invention, which is a spice simulation waveform, where A waveform is a crosstalk generation waveform between channels when a buffer is not used in the prior art, and B waveform is according to the present invention. When supplying a common base bias using a buffer, crosstalk can be significantly reduced by supplying a common base bias using a buffer according to the present invention as a crosstalk generation waveform between channels.

As described above, the present invention can significantly reduce crosstalk since the common base bias of each amplifier is supplied through the buffer, and is particularly useful when controlling three amplifier circuits with one bias circuit in a wide-band amplifier. Do.

Claims (1)

A common base bias of the differential amplification transistors Q2, Q3, Q5, Q6, and Q8 and Q9 of each amplification circuit is supplied from the bias circuit 4 which is bias-controlled by the variable resistor V _R1 . R, G, B signals (Rin), (Gin), (Bin) are inputted through emitter transistors (Q1), (Q4), (Q7), and the differential amplifier transistors (Q3), (Q6), (Q9). In the R, G, B amplification circuits (1), (2), and (3) configured to perform R, G, and B outputs (Rout), (Gout), and (Bout) through the bias circuit (4). Emitters of transistors Q11, Q13, Q21, Q23, and Q31 and Q33 to which the bias outputs V1 and V2 are applied to the base, respectively, and the differential amplifier transistors Q2 and Q3 and Q5. , Q6) and (Q8, Q9) and the emitters of the transistors (Q11), (Q21) and (Q31), respectively, through the resistors (R11), (R21) and (R31) Common connections are made to the collectors and bases of the transistors Q12, Q22, and Q32. Bias buffers 11, 12, and 13 which connect the connected collectors of the power supply transistors Q14, Q24, and Q34 to the emitter connection points of the transistors Q13, Q23, and Q33. R, G, B signal amplification circuit comprising a) configuration comprising.