FR2524747A1 - DEVICE FOR ADJUSTABLE SIGNAL BUILDING - Google Patents

Abstract

THE INVENTION RELATES TO A SYSTEM FOR PRODUCING AN ADJUSTABLE AMOUNT OF SIGNAL DIGGING DERIVED FROM A SOURCE. ACCORDING TO THE INVENTION, THE SYSTEM INCLUDES A FIRST SIGNAL TRANSLATION MEANS, A SECOND SIGNAL TRANSLATION MEANS, WHICH INCLUDES A MULTI-STAGE LIMITER AMPLIFIER INCLUDING FIRST 50 AND SECOND 60 STAGE SIGNAL AMPLIFIERS COUPLED IN CASCADE AND PRESENT A TOTAL GAIN SENSITIVELY EQUAL TO THE GAIN PRESENTED BY THE FIRST SIGNAL TRANSLATION MEANS; A MEANS DEVELOPING AN INGREEN VERSION RESPONDING TO THE OUTPUTS OF THE MEANS OF TRANSLATION; AND A WAY TO VARY THE DC GAIN DISTRIBUTION, 61, 65, 67, 68 CONNECTED TO THE AMPLIFIER STAGES TO MODIFY THE GAIN DISTRIBUTION BETWEEN THE FIRST AND SECOND AMPLIFIER STAGES WITHOUT DISTURBING THE TOTAL GAIN OF THE LIMITER AMPLIFIER. THE INVENTION APPLIES IN PARTICULAR TO TELEVISION.

Description

The present invention relates generally to

  adjustable signal digging circuits, and in particular

  to new digging circuits of an adjustable type allowing the control of the digging level, with the removal of the heart of the signal obtained precisely

  at a number of different levels of digging.

  The digging of a signal (that is, the removal of a "heart" of the signal close to the axis, by the signal processing with a translation means having a transfer characteristic with a dead zone for signal excursions near the axis) is a known signal processing function, which is occasionally used for noise reduction purposes, as explained, for example, in an article by JP Rossi entitled " Digital Techniques for Reducing Television Noise ", published on pages 134-140 of the March 1978 edition of the SMPTE Journal In some uses of a digging circuit, it may be desirable to have an opportunity to adjust the level of digging to This possibility may allow a manual adjustment of the level of digging (as shown for example in an article by RH McMann and others, entitled "Improved Signal Processing Techniques for Color Television Broadcasting" published by pages 221-228 of the March 1968 edition of the SMPTE Journal), or may allow dynamic adjustment of the level of digging (as indicated, for example, in US Pat. No. 4,167,749 to Burrus, where digging varies depending on the level of detected noise

  as accompaniment to a video signal).

  The present invention relates to a digging circuit

  of a type allowing the adjustment of the level of hollow

  but avoids the need for capacitive elements in

  its structure, and which can be easily and efficiently

  In the use of such a digging circuit, the end of the minimum digging level of the digging level adjustment may allow a defined residual level of digging. According to the principles of the invention, a signal to be digged is applied to the input of a linear signal translation means and to the input of a translation means.

  signal, the latter comprising an amplification

  multi-stage limiter circuit for developing a doubly limited version of the signals, and having a total gain substantially equal to the gain presented by the linear signal translation means The amplifier

  limiter comprises first and second stages amplifying

  signal transducers which are cascaded for signal amplification purposes A combination means of

  signals, responding to the outputs of the two means of transla-

  tion, develops an in-ground version of the corresponding signals

  difference between a linearly transla-

  Signal output and a limited version of the signals To obtain a leveling adjustment, means are coupled to the cascade amplifier stages of the limiter amplifier to modify the gain distribution between them substantially without disturbing the gain.

total of the limiter amplifier.

  According to an embodiment of the present invention, the cascade amplifier stages of the limiter amplifier comprise respective differential amplifiers, each deriving its operating current from the collector of a respective transistor forming a current source. The base-emitter paths of the transistors current-forming sources are connected in series to a common source of bias The variation of a variable DC impedance which is connected in shunt with the base-emitter path of one of the current-source transistors performs the control Desired level of digging As an example, the variable DC impedance comprises the collector-emitter path of a first control transistor

  having an adjustable polarized base-transmitter junction.

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  In an exemplary use of the present invention, the signal that is subjected to adjustable digging is an accent signal derived from the luminance component

  of a television signal for use in the accentuation

  tion of a horizontal detail in the reproduction of a

  In such a use of the invention, the signal of acceleration

  tionally dug death is advantageously

  followed by an automatic adjustment system.

  closed-loop tick to substantially prevent adjustments in the level of emphasis

  to have undesirable effects on the level of

obtained.

  According to another modification of the invention, the above-described digging system may make it possible to automatically obtain the extinction of the digging action at the end of the minimum digging level.

  the setting range of the digging level.

  In this modification, the digging level adjustment system uses a second transistor of

  control in addition to the first control transistor

  described above, the respective control transistors having opposite types of conductivity The emitter of the second control transistor is connected to the base of

  one of the current source transistors of the amplifier

  and the emitter-collector path of the second control transistor is shunted through the series combination of the base-emitter paths of the two current-source transistors. The base of the second control transistor is made responsive to the same control-level voltage. digging that used to adjustably bias the first control transistor over much of the range

  the level of digging, the base-emitter junction

  In such circumstances, the second control transistor is turned off and the adjustable digging operation is not affected. In the vicinity of the minimum end of the digging level of the control range. however, the base-emitter path of the second control transistor is directly biased A strong conduction of the second control transistor when the minimum end of the digging level of the digging level setting range is reached produces an inhibition of the limiter amplifier,

  allowing the extinction of the digging action.

  The invention will be better understood and other purposes,

  characteristics, details and advantages of it

  more clearly in the explanatory description

  which will follow with reference to the accompanying schematic drawings given by way of example illustrating an embodiment of the invention and wherein: Figure 1 illustrates by block diagram, a digging circuit according to the present invention; FIG. 2 illustrates, partially schematically and partially in the form of a block diagram, an example of an implementation of the digging circuit of FIG. 1 to obtain an adjustable digging of an accent signal in a television set; and FIG. 3 illustrates, in block diagram form, an automatic adjustment system of accentuation with which the device of FIG. 2 can advantageously

to be associated.

  In the system of FIG. 1, the signals of a source 11 are applied to the inputs of a linear amplifier 13 and of a multi-stage limiter amplifier 15 The magnitude of the total gain (+ G 1) produced by the amplifier limit to several floors 15 is equal

  in the magnitude of the gain (-G 1) of the linear amplifier 13.

  The outputs of the respective amplifiers are in phase opposition relation, the linear amplifier 13 for example, producing a net phase inversion while

  that the limiter amplifier 15 does not reverse it.

  The output of the linear amplifier 13 is a linearly translated version of the input signals, while the limiter amplifier 15 serves as nonlinear translation means of signals producing a doubly clipped version of the received signals. The addition of the outputs of the amplifiers 13, 15 is effected by signal combining means 17 to form an in-ground version of the input signals for

  application to a signal utilization circuit 19.

  The waveform of the dug signals applied to the utilization circuit 19 corresponds to the waveform of the received signals minus the central "heart" close to the axis, which has been

  removed by cancellation in the combining means 17.

  The distribution of the gain between the cascaded stages of the multi-stage limiter amplifier 15 is adjusted by a gain distribution control circuit 23 in response to an adjustment or control voltage developed by a source of power. variable digging adjustment voltage 21, substantially without

  disrupt the total gain of the limiter amplifier 15.

  A practical technique for changing the gain distribution between cascaded stages of the multi-stage amplifier is disclosed, for example, in the US Patent Application entitled "Amplifier Incorporating Gain Distribution Control for Cascaded Amplifying Stages".

  No. 363,869 filed March 31, 1982.

  While the gain distribution between the cascaded input and output stages of the amplifier 15 is changed in response to a variation of the set voltage applied by the source 21, the relative magnitude of the core being removed In fact, the depth or the level of digging of the input signals is adjusted in response to a variation of the digging adjustment voltage. A change in the distribution of the gain which increases the gain of the stage. input results in clipping by the output stage which is closer to the axis, and thus reduces the level of excavation Conversely, a change in gain distribution which decreases the gain of

6 2524747

  the input stage increases the level of digging The maintenance of the total gain of the amplifier 15 has a substantially constant value with respect to the gain distribution changes however ensures the correspondence relation between the parts of the waveforms of the amplifiers. inputs of the combination means 17 necessary for a precise cancellation to produce a dig at the chosen level. In FIG. 2, an example of an embodiment of the digging system of FIG. 1 is illustrated in FIG.

  schematic detail, which performs the function of digging

  In the embodiment of FIG. 2, a differential amplifier 40 serves as a linear amplifier of the system of FIG. 1, and the differential amplifiers 50 and 60 serve as stages. cascade input and output of the multiple limiter amplifier

stages of the system of Figure 1.

  To develop the accent signal that must be processed by a montage according to the principles of lalresente

  invention, the output of a source of light signals

  nance (for example in a use in a color television, constituted by the luminance signal at the output of the comb filter of the television set), is connected by a resistor 27 to the input terminal (L) of a delay line

  By way of example, the delay line 29 is a device

  broadband signal which has a linear phase characteristic over the frequency range occupied by the signals of the source 25 (e.g.

  4.0 MHz), which produces a signal delay of 140 nano-

  seconds The input end of the delay line 29 is terminated (for example using the resistor 27) by an impedance substantially matched to its characteristic impedance, while the output end of the delay line ( at the terminal L ') is poorly terminated to obtain a reflective effect The signals appearing at the respective ends of the delay line 29 are thus

7 2524747

  (a) a luminance signal when delayed at the L 'terminal, and (b) the sum of a non-delayed luminance signal and a twice delayed luminance signal at the L terminal. The difference between the signals at the terminals L and L 'corresponds to an appropriate signal of horizontal accentuation for addition to the luminance signal in order to

  to improve its horizontal detail (by increasing

  the luminance components in a frequency range

  from 1.75 M Hz to 5.25 M Hz, points to -6 dB, with a

maximum increase at 3.5 M Hz).

  A differential amplifier 40, receiving the signals

  terminals L and L 'at its respective differential inputs

  Ves forms a linear amplification channel for such an accent signal Amplifier 40 comprises two

  transistors 41, 43 of the NPN type with international transmitters

  connected to a reference potential point (such as ground) by the collector-emitter path of an NPN-type current source transistor 45

  series with transmitter resistance 46 The basis of the transis-

  tor 45 is connected to the positive terminal (+ 1.2 volts) of a bias potential power source to set a desired operating current for

the amplifier 40.

  The signals of the terminal L 'are applied at the base

  transistor 41 by the base-emitter path of a transistor

  tor 34 of the NPN type mounted as a follower and a series coupling resistor 36 The collector of the

  transistor 34 is directly connected to the positive terminal

  ve (+ Vcc) of a power supply operating current, while the emitter of the transistor 34 is grounded by the collector-emitter path of a transistor 35 forming a current source (whose base is connected to the + 1.2 V bias supply terminal) in series with the transmitter resistor 26

  L-terminal signals are applied at the base of the transis-

  tor 43 through the base-emitter path of an emitter-follower transistor NPN-type transistor 30 and a series coupling resistor 32 The collector of transistor 30 is directly connected to the power supply terminal + Vcc, while The emitter of transistor 30 is grounded by the collector-emitter path of a current source transistor 31 (whose base is connected to the + 1.2 V bias supply terminal) in series with the resistor. While direct connections are illustrated between the respective terminals L, L 'and the bases of the transistors 30, 34 as a follower, additional tracking emitters (not shown) may advantageously be interposed in the respective connections to increase impedances

  presented at the respective terminals.

  A resistor 38 interconnects the bases of the transistors 41, 43 and cooperates with the coupling resistors 36, 32 to introduce a degree of attenuation of the input signals which ensures that the maximum difference between the base potentials will be within

  the linear range of signal processing of the amplification

  40 The respective collectors of transistors 41 and

  43 are related to the positive terminal of a power source.

  The respective collector currents of transistors 41 and 43 vary according to the opposing phase versions of the accent signals. The differential amplifier 50, receiving the signals

  terminals L and L 'at its respective differential inputs

  The amplifier 50 comprises two transistors 51, 53 of the NPN type with interconnected transmitters which are connected to the amplifiers. the mass via the collector-emitter path of a NPN-type current source transistor 55. The signals of the terminal L ',

  appearing at the output of transistor 34 as a transmitter

  follower, are applied to the base of the transistor 51 by a series coupling resistor 37 The signals of the terminal L, appearing at the output of the emitter-follower transistor 30 are applied to the base of the transistor 53 by a coupling resistor series 33 One

  Resistor 39 connects the bases of transistors 51 and 53.

  The attenuation of the input signals produced by the network

  resistances 37, 39, 33 is smaller than the attenuation

  generated by the linear amplifier array (36, 38, 32) and allows the maximum oscillation of the signal between the bases to exceed the linear processing range of

signals from the amplifier-Ocateur 50.

  The collectors of transistors 51 and 53 are indivi-

  connected by respective load resistances (57, 59) to the positive (+ 4.0 V) terminal of a power source at the operating potential. Oppressive emphasis signals (with maximum clipped excursions) ) appear in the resistors

load ratios 57 and 59.

  The differential amplifier 60, serving as an output stage of the limiter amplifier and producing further clipping of the boosting signals, comprises two NPN transistors 61 and 63 whose emitters are connected to the collectors of a transistor 65. The emitter of transistor 65 is grounded by the base-emitter path of current source transistor 55. The base of transistor 61 is directly connected to the collector of transistor 51 of the input stage. that the base of transistor 63 is directly connected to the collector of transistor 53

from the entrance floor.

  The collector of the transistor 61 is directly connected to the collector of the transistor 41 of the linear amplifier, so the combined collector currents of the

  transistors 41 and 61 form an amplification signal current.

  The collector of the transistor 63 is directly connected to the collector of the transistor 43 of the linear amplifier so the collector added currents of the transistors 43 and 63 form an accented signal current Ip (in opposition to FIG.

phase with Ip ').

  A resistor 66 is connected between the positive terminal (+ 3.2 V) of a power source at the bias potential and the anode of a diode 67, whose cathode

  is directly connected to the anode of a second diode 68.

  The cathode of the diode 68 is directly connected to ground, so the two diodes 67, 68 are forward biased

  by the power source to the bias potential.

  The anode of the diode 67 is directly connected to the base of the current source transistor 65, so the voltage appearing in the pair of diodes (67, 68) is applied to the serial transmitting-transmitting objects forming the current sources 65, 55 , to polarize live

their base-emitter junctions.

  The collector of an additional transistor 71 of the type

  NPN is directly connected to the base of transistor 55.

  The emitter of transistor 71 is directly connected to ground, putting the collector-emitter path of transistor 71 directly in shunt with the base-emitter path of

  transistor 55 forming current source of the input stage.

  A DC digging adjustment voltage input terminal is connected to the base of a NPN transistor 75

  mounted in transmitter-follower (whose collector is direct-

  The emitter of the transistor 75 is connected by a resistor 73 to the base of the transistor 71 and to the anode of a diode 72. The cathode of the diode 72 is directly connected to the diode 72. the ground, which puts the diode 72 directly in shunt with the base-emitter path of the transistor 71 A positive set regulation voltage applied to the terminal CC adjusts the bias of the transistor 71 to vary the conductance of its collector-emitter path and thus adjust the level of digging reached in the current of the

output signal Ip and Ip '.

  A control transistor 69 of the PNP type is arranged with its emitter directly connected to the base of the transistor 65 forming a current source. The collector of the transistor 69 is brought back directly to ground, which puts the emitter-collector path of the transistor 69. directly in shunt with the serial combination of the base-emitter paths of the two source-forming transistors

  current 65, 55 The base of transistor 69 is directly

  connected to the set voltage input terminal

CC digging.

  The digging adjustment voltage source is illustrated in the drawings as a manually adjustable potentiometer 21, whose adjustable tap is directly connected to the DC terminal and whose fixed end terminals are respectively connected to the positive (+ V) terminal. ) as a example, the potential at the + V terminal is considerably larger than the potential (2 Vbe) developed in the series combination of the diodes 67, Thus, the base-emitter junction of the PNP-type transistor 69 remains reverse-biased over a large part of the input range (when the setting potential chosen by the tap exceeds the potential of 2 Vbe). Variable voltage Digging adjustment can also be produced by a dynamic tuning source (as in the aforementioned Burrus patent, for example) over much of the adjustment range, the transist The PNP control type 69 is cut off, and the operation of the adjustable digging system is as indicated immediately below. The base-emitter path of transistor 65 forms a voltage divider with the parallel combination of (a) the base-emitter path of transistor 55, and (b) the collector-emitter path of transistor 71, to effect a division of voltage polarization occurring in the series diodes 67, 68, the ratio

12 2524747

  IEC 60050 - International Electrotechnical Vocabulary - Details for IEV number 845-07-21 Circuit technology / Electromagnetic compatibility of the NPN-type control transistor 71 When the shunt impedance of the transistor 71 decreases (because of an increase in the digging adjustment voltage), the base-emitter voltage (Vbe) of the current source transistor 55 decreases, accompanied by a complementary increase of the base-emitter voltage of the current source transistor When the shunt impedance presented by the transistor 71 increases (due to a decrease in the voltage of the digging adjustment), the Vbe of transistor 65 increases, accompanied by a decrease

  complementary to the Vbe of transistor 65.

  The variation of the digging adjustment tension thus results in an intxduction of variations

  complementary to the operating currents of amplifi-

  differentiators 50 and 60 and, consequently,

  complementary to the respective gains of the two stages in cascade of the limiter amplifier With a variation

  dc impedance presented by the transistor

  tor 71 having a negligible effect on the voltage of

  between the diodes 67, 68, the total gain of the limiting amplifier, proportional to the product of the quantities of the respective currents of the stages, remains substantially undisturbed while the distribution

  between the respective stages varies.

  s sion of digging, this undisturbed magnitude of gain

  total is established in such a way that the

  nonlinear and linear amplification

substantially identical.

  A change in gain distribution (caused by a decrease in digging adjustment voltage) which raises the gain of the input stage (50) results in clipping, by the output stage (60) which is more

  close to the axis, and thus reduces the level of digging.

  Conversely, a change in gain distribution (caused by an increase in digging adjustment voltage) that lowers the gain of the input stage

13 2524747

increases the level of digging.

  While the position of the adjustable tap approaches the end terminal at the ground of the potentiometer 21, however, the bias of the base-emitter junction of the PNP control transistor 69 changes to the direct direction and conduction in the path The emitter-collector of the transistor 69 occurs at the end of the adjustment range which sets the tap to the potential of the mass, this conduction is sufficiently large to result in a break of the transistors 65, 55 forming current sources, and a

  consequent extinction of the digging of the acceleration signals

horizontal slaughter.

  Figure 3 illustrates an additional signal processing device with which the digging means

  of accentuation signals of FIG. 2 may advantageously

  In Figure 3, the accentuation signals

  push-pull (Ip and Ip ') at the output of the system of FIG. 2 are applied as inputs to a gain amplifier amplifier 101

  The amplifier 101 translates the accent signals

  with a gain (attenuation) which is determined by a control voltage applied to the terminal

PC accent setting.

  The push-pull outputs of the amplifier 101 are added to the push-pull outputs of a luminance signal amplifier, responding to the delayed luminance signals at the terminal L '(FIG. 2), in a combination means of signals 103 to form push-pull versions of an accentuated luminance signal for application to an amplifier 107 of accentuated luminance signals The amplifier 107 converts the accentuated signals into luminance push-pull which it receives in an asymmetrical form at the output terminal 0, where the enhanced luminance signal can be applied, for example, to matrix circuits of the color television for combination with respective color difference signals. The output of the amplifier 107 is also applied to the input of a band-pass amplifier 109 for automatic adjustment of the emphasis. As an example, a bandwidth with a width of approximately 1 M Hz centered on At a frequency of approximately 2 M Hz, the amplifier 109 delivers the components of the accentuated luminance signal in its bandwidth to a peak detector 110 which develops a voltage of 1 o regulates the amplitude of the components delivered. adjustment is applied to the PC terminal to adjust the magnitude of the accent signals

  applied by means of combination 103 in a sense that

  These modifications are described in US Pat. No. 310,139, filed October 9, 1981, for a more detailed explanation of the operation of such an automatic accent control system, and examples of such modifications. an advantageous arrangement for the implementation of the functions of elements 101, 103, 105, 107, 109 and 110

  (as well as the combination of a manual accent setting).

  The advantage of the combination of the device of FIG. 3 with the adjustable digging system of FIG. 2 lies in the fact that it is possible to substantially avoid any detrimental effect on the level of accentuation when the level of digging is adjusted. illustrate this point, consider, for example, that a change in

  digging adjustment voltage is performed to increase

  the level of digging to increase the removal

  This increased removal of the core is accompanied, therefore, by a reduction in the amplitude of the retained components of the accent signal at the output of the system of FIG. The automatic emphasis control system of FIG. 3, however, will tend to oppose any weakening of the accentuation effects

2524747

  amplitude reduction may otherwise cause by introducing a compensation change in the

gain of the amplifier 101.

  An example of values for the system circuit parameters of FIG. 2 is given below: Resistors 26, 28 2 kilohms Resistance 27 680 ohms Resistors 32.36 2.4 kilohms Resistors 33.37 470 ohms Resistance 38 1000 ohms Resistance 39 4.7 ohms Resistors 46.57.59 500 ohms Resistance 66 13.3 kilohms Resistance 73 25 kilohms Potential (+ Vcc) 11.2 volts

Claims (10)

R E V E N D I C A T I 0 N S   System for producing an adjustable amount of digging of signals derived from a source, characterized by first signal translation means (13)   having an input coupled to said source, for translating   linear representation of said signals; second signal translation means (15) having an input coupled to said source for non-linear translation of said signals; said second signal translation means including a multi-stage limiter amplifier for developing a limited version of said signals, said limiter amplifier   comprising first (50) and second (60) amplifier stages   signal drivers coupled in cascade, and having a total gain which is substantially equal to the gain presented by said first signal translation means;   means developing a dug version (17)   at the outputs of said first and second transmission means   signal generation, for developing a dug-out version of said signals corresponding to the difference between a linear translation version of said signals and a limited version of said signals; and a gain varying means (CC 71, 65, 67, 68) coupled to said first and second signal amplifier stages for selectively varying the gain distribution between said first and second   signal amplification stages substantially without   ber the total gain of said limiter amplifier.   2 System according to claim 1, characterized in that one (13) of the above-mentioned means of signal translation, to the exclusion of the other, subjects said signals to a net phase inversion, and in that the means aforesaid developing the dug signals comprises means (17) for adding the outputs of said first (13)   and second (15) signal translation means.   System according to Claim 1, characterized in that the aforementioned source is a source (25) of luminance signals and the signals translated in the first (13) and second (15) signal translation means comprise accent signals. derivatives   of said source of luminance signals.   A system according to claim 2, characterized by a tuned gain boost signal amplifier (101) responsive to the output of said means for developing a dug-out version (17);   means (103) for combining the output of said amplifier   a gain emphasis signal controller set to luminance signals derived from said source to form an increased output luminance signal; and means (107, 109, 110) responsive to said increased output luminance signal for adjusting the gain of said   accent signal amplifier.   A system according to claim 4, characterized in that said gain adjusting means comprises a selective frequency amplifier (109) having an input coupled to receive the output enhanced luminance signal, said amplifier having a bandwidth containing a portion of high frequency of the frequency spectrum occupied by said luminance signals; and a peak detector (110) responsive to the output of said amplifier for developing a gain adjustment voltage. System according to Claim 1, characterized in that the aforesaid source is a source (105) of luminance signals in a television set; a delay line (29) has its input coupled to said source of luminance signals; the aforementioned first signal translation means (13) comprises a linear means   signal translation system comprising a first amplifier   differential encoder (40) having two inputs coupled to respond to signals appearing at the input (L) of said delay line (29) and the signals appearing at the output (L ') of said delay line, respectively; said second signal translation means (15) comprises a nonlinear signal translation means comprising a limiter amplifier comprising second (50) and third (60) differential amplifiers coupled in cascade, said second differential amplifier having two inputs coupled to respond to signals appearing at the input (L) of said delay line (29) and the signals appearing at the output (L ') of said delay line, respectively; said gain distribution variation means is coupled to said second (50) and third (60) differential amplifiers for simultaneously   vary the gains of said second and third amplifiers.   Differentially different emitters; the total gain of said nonlinear signal translation means being independent of the operation of said means varying the gain distribution and substantially equal to the gain of said linear signal translation means; the aforesaid means developing a hollow version (17) combines the outputs of said linear signal translation means and said non-linear translation means   line of signals to form a signal dug out of   the level of digging depends on the functioning   said means varying the gain.   The system of claim 6, characterized by a tuned gain boosting signal translation means (101) responsive to said ducked boost signal; means (103) for combining the output of said tuned gain boost signal translation means with the luminance signals derived from said source (105) to form an enhanced luminance signal; a frequency selector amplifier (109) having an input responsive to said enhanced luminance signal and having a bandwidth containing a region of 19247477   high frequencies of the frequency band occupied by said luminance signal; and means (110) responsive to the output amplitude of said frequency selector amplifier for controlling the gain of said Uon signal translation means. System according to claim 1, characterized in that the aforesaid means developing an in-ground version comprises a bias voltage source (3.2 V) a first current source transistor (55) has a base, an emitter and a collector for supplying an operating current to the amplifier stage said entrance (50); -   a second current source transistor (65) has a base, an emitter and a collector for supplying an operating current to said output amplifier stage (60); the respective base-emitter paths of said first and second current source transistors are   connected in series to said polarization voltage source   tion; first (71) and second (69) transistors of   order each have a base, a transmitter and a collection   and, they are of mutually opposite conductivity types, the collector-emitter path of said first control transistor (71) is shunt connected with the base-emitter path of said first current source transistor (55); the collector-emitter path of said second control transistor (69) is shunt connected with the series combination of the base-emitter paths of said first and second current source transistors; a source (21) of variable DC voltage; and means (CC, 75) for making the bases of said first and second control transistors responsive to a variable DC voltage. 2524747   System according to claim 8, characterized in that the polarity of the variable DC voltage (21) is such that it effects a variable direct bias of the base-emitter junction of the aforementioned first control transistor (71). System according to claim 9, characterized in that the range of the variations of the variable DC voltage is such that the aforesaid second control transistor (69) is maintained in a non-conductive state in response to values of said variable DC voltage.   over a major part of said range of variations.   System according to any one of the claims   8 to 10, characterized in that the aforementioned transistors (55, 65) forming current sources have the same type   of conductivity (NPN) than the first Mande (71) supra.   The system of claim 11, characterized in that each of said amplifier stages comprises a differential amplifier (50, 60) having two transistors (51, 53; 61, 63) of the same conductivity type as said first control transistor, with interconnected transmitters connected to the collector   of a respective transistor forming a current source.