GB2081187B - Retro-etch process for integrated circuits - Google Patents

Retro-etch process for integrated circuits

Info

Publication number
GB2081187B
GB2081187B GB8121901A GB8121901A GB2081187B GB 2081187 B GB2081187 B GB 2081187B GB 8121901 A GB8121901 A GB 8121901A GB 8121901 A GB8121901 A GB 8121901A GB 2081187 B GB2081187 B GB 2081187B
Authority
GB
United Kingdom
Prior art keywords
retro
integrated circuits
etch process
etch
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB8121901A
Other languages
English (en)
Other versions
GB2081187A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EMC Corp
Original Assignee
Data General Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Data General Corp filed Critical Data General Corp
Publication of GB2081187A publication Critical patent/GB2081187A/en
Application granted granted Critical
Publication of GB2081187B publication Critical patent/GB2081187B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H10D64/0133—Aspects related to lithography, isolation or planarisation of the conductor at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing
GB8121901A 1980-07-21 1981-07-16 Retro-etch process for integrated circuits Expired GB2081187B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/170,833 US4318759A (en) 1980-07-21 1980-07-21 Retro-etch process for integrated circuits

Publications (2)

Publication Number Publication Date
GB2081187A GB2081187A (en) 1982-02-17
GB2081187B true GB2081187B (en) 1984-03-07

Family

ID=22621451

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8121901A Expired GB2081187B (en) 1980-07-21 1981-07-16 Retro-etch process for integrated circuits

Country Status (6)

Country Link
US (1) US4318759A (https=)
JP (1) JPS5787136A (https=)
DE (1) DE3128629A1 (https=)
FR (1) FR2487125A1 (https=)
GB (1) GB2081187B (https=)
IT (1) IT1138064B (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2496982A1 (fr) 1980-12-24 1982-06-25 Labo Electronique Physique Procede de fabrication de transistors a effet de champ, a grille auto-alignee, et transistors ainsi obtenus
US4546066A (en) * 1983-09-27 1985-10-08 International Business Machines Corporation Method for forming narrow images on semiconductor substrates
US4631113A (en) * 1985-12-23 1986-12-23 Signetics Corporation Method for manufacturing a narrow line of photosensitive material
US4906585A (en) * 1987-08-04 1990-03-06 Siemens Aktiengesellschaft Method for manufacturing wells for CMOS transistor circuits separated by insulating trenches
DE3817326A1 (de) * 1988-05-20 1989-11-30 Siemens Ag Verfahren zur herstellung von gitterstrukturen mit um eine halbe gitterperiode gegeneinander versetzten abschnitten
DE3915650A1 (de) * 1989-05-12 1990-11-15 Siemens Ag Verfahren zur strukturierung einer auf einem halbleiterschichtaufbau angeordneten schicht
EP0518418A1 (en) * 1991-06-10 1992-12-16 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device whereby field oxide regions are formed in a surface of a silicon body through oxidation
DE10052955A1 (de) * 2000-10-25 2002-06-06 Tesa Ag Verwendung von Haftklebemassen mit anisotropen Eigenschaften für Stanzprodukte
ITMI20042243A1 (it) * 2004-11-19 2005-02-19 St Microelectronics Srl Processo per la realizzazione di un dispositivo mos di potenza ad alta densita' di integrazione
US7875936B2 (en) * 2004-11-19 2011-01-25 Stmicroelectronics, S.R.L. Power MOS electronic device and corresponding realizing method
FR2880471B1 (fr) * 2004-12-31 2007-03-09 Altis Semiconductor Snc Procede de nettoyage d'un semiconducteur
CN111696912B (zh) * 2019-03-12 2025-02-25 长鑫存储技术有限公司 半导体结构及其形成方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1559608A (https=) * 1967-06-30 1969-03-14
NL157662B (nl) * 1969-05-22 1978-08-15 Philips Nv Werkwijze voor het etsen van een oppervlak onder toepassing van een etsmasker, alsmede voorwerpen, verkregen door toepassing van deze werkwijze.
US3764865A (en) * 1970-03-17 1973-10-09 Rca Corp Semiconductor devices having closely spaced contacts
DE2139631C3 (de) * 1971-08-07 1979-05-10 Deutsche Itt Industries Gmbh, 7800 Freiburg Verfahren zum Herstellen eines Halbleiterbauelements, bei dem der Rand einer Diffusionszone auf den Rand einer polykristallinen Siliciumelektrode ausgerichtet ist
US4124933A (en) * 1974-05-21 1978-11-14 U.S. Philips Corporation Methods of manufacturing semiconductor devices
JPS5131186A (https=) * 1974-09-11 1976-03-17 Hitachi Ltd
US4063992A (en) * 1975-05-27 1977-12-20 Fairchild Camera And Instrument Corporation Edge etch method for producing narrow openings to the surface of materials
GB1543845A (en) * 1975-05-27 1979-04-11 Fairchild Camera Instr Co Production of a narrow opening to a surface of a material
US3966514A (en) * 1975-06-30 1976-06-29 Ibm Corporation Method for forming dielectric isolation combining dielectric deposition and thermal oxidation
US4040168A (en) * 1975-11-24 1977-08-09 Rca Corporation Fabrication method for a dual gate field-effect transistor
US4053349A (en) * 1976-02-02 1977-10-11 Intel Corporation Method for forming a narrow gap
US4239559A (en) * 1978-04-21 1980-12-16 Hitachi, Ltd. Method for fabricating a semiconductor device by controlled diffusion between adjacent layers
DE2902665A1 (de) * 1979-01-24 1980-08-07 Siemens Ag Verfahren zum herstellen von integrierten mos-schaltungen in silizium-gate- technologie

Also Published As

Publication number Publication date
FR2487125B1 (https=) 1984-04-20
FR2487125A1 (fr) 1982-01-22
GB2081187A (en) 1982-02-17
JPS5787136A (en) 1982-05-31
DE3128629A1 (de) 1982-06-09
US4318759A (en) 1982-03-09
IT1138064B (it) 1986-09-10
IT8122944A0 (it) 1981-07-15

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee