GB1473706A - Noise suppressor circuit - Google Patents

Noise suppressor circuit

Info

Publication number
GB1473706A
GB1473706A GB2851274A GB2851274A GB1473706A GB 1473706 A GB1473706 A GB 1473706A GB 2851274 A GB2851274 A GB 2851274A GB 2851274 A GB2851274 A GB 2851274A GB 1473706 A GB1473706 A GB 1473706A
Authority
GB
United Kingdom
Prior art keywords
input
gate
level
input signal
stable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2851274A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Priority to GB2851274A priority Critical patent/GB1473706A/en
Publication of GB1473706A publication Critical patent/GB1473706A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/013—Modifications of generator to prevent operation by noise or interference

Abstract

1473706 Pulse width discriminating circuits STANDARD TELEPHONES & CABLES Ltd 27 June 1974 28512/74 Heading H3T A noise suppression circuit comprises: a first MOS two-input AND gate 9 to the inputs of which a sampling input signal IP2 and a further input signal IP1 to be compared are applied; a first bi-stable 3, 4 having one input connected to the output of gate 9 and its outputs connected to respective first inputs of further two-input AND gates 7, 8; a second bistable 5, 6 having its inputs connected respectively to the outputs of gates 7, 8; and the input signal IP2 being also applied to a second input of gates 7, 9. A first sample pulse prepares gate 9 so that a "1" level input signal will pass through it to set bi-stable 3, 4 preparing gate 8. If the input "1" level persists sufficiently long for a second sample pulse to arrive, this pulse will pass through gate 8 to set bi-stable 5, 6 and produce an output. If the input "1" level ceases before the next sampling pulse the resulting "0" level is inverted by NOR gate 2 to reset bistable 3, 4. When the bi-stables are both set, the circuit will similarly distinguish between long and short "0" conditions of the input signal, that is bi-stable 5, 6 will only reset if a "0" level condition is sufficiently long to span at least two sampling pulses.
GB2851274A 1974-06-27 1974-06-27 Noise suppressor circuit Expired GB1473706A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB2851274A GB1473706A (en) 1974-06-27 1974-06-27 Noise suppressor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2851274A GB1473706A (en) 1974-06-27 1974-06-27 Noise suppressor circuit

Publications (1)

Publication Number Publication Date
GB1473706A true GB1473706A (en) 1977-05-18

Family

ID=10276818

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2851274A Expired GB1473706A (en) 1974-06-27 1974-06-27 Noise suppressor circuit

Country Status (1)

Country Link
GB (1) GB1473706A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2420249A1 (en) * 1978-03-17 1979-10-12 Siemens Ag DIGITAL SEMICONDUCTOR DEMODULATOR

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2420249A1 (en) * 1978-03-17 1979-10-12 Siemens Ag DIGITAL SEMICONDUCTOR DEMODULATOR

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Legal Events

Date Code Title Description
PS Patent sealed
435 Patent endorsed 'licences of right' on the date specified (sect. 35/1949)
PCNP Patent ceased through non-payment of renewal fee