GB1338241A - Apparatus for testing delay units - Google Patents

Abstract

1338241 Testing delay units MARCONI CO Ltd 4 May 1971 [23 July 1970] 35771/70 Heading G1U In order to test a delay unit 1, Fig. 1, a pulse is applied simultaneously both to it and to two other delay units 2, 3 accurately adjusted to have delays corresponding to the upper and lower tolerances appropriate to the delay unit under test, and means are provided for determining whether the pulse eventually emitted by the delay unit under test occurs within or outside the tolerance range. As described a 'one' signal is normally applied to all three delay units by a bistable circuit 6, 7 causing, as a result, the signal combination '1, 0' to be applied to the upper and lower inputs respectively of two triggers 14, 15. In operation a push-button 10 is momentarily depressed to change the state of bistable circuit 6, 7 causing a 'zero' to be entered into all three delay units and causing the triggers 14, 15 each to assume the signal condition applied to their inputs namely 1,0. The triggers 14, 15 are such that when a 'zero' signal is applied to their central inputs 23, 24 respectively, they assume as their stable conditions, states corresponding to the signal combinations applied to them by delay units 2 and 3. Thus, if the delay unit under test produces a 'zero' output in response to the 'zero' input before the lower threshold delay 2 does, then neither trigger 14, 15 changes its state, their states remaining 1,0. However, if the 'zero' output from the delay unit under test occurs after that from the lower threshold delay 2, then it will find the signal combination 0,1 applied to trigger 14, which as a result, will change its state to produce a 0,1 signal combination output. Similarly, if the output from the delay unit under test occurs after that from the upper tolerance delay 15, then both triggers change their states. The output signals from triggers 14 and 15 are decoded by NAND gates 27, 28, 29 to control lamps indicating "too short", "too long" and "OK", gates 27, 28, 29 normally being inhibited by a 'one' signal from the delay unit under test.