GB1445592A - Insulated layers - Google Patents

Insulated layers

Info

Publication number
GB1445592A
GB1445592A GB1428873A GB1428873A GB1445592A GB 1445592 A GB1445592 A GB 1445592A GB 1428873 A GB1428873 A GB 1428873A GB 1428873 A GB1428873 A GB 1428873A GB 1445592 A GB1445592 A GB 1445592A
Authority
GB
United Kingdom
Prior art keywords
layer
substrate
compressed
assembly
march
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1428873A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Priority to GB1428873A priority Critical patent/GB1445592A/en
Priority to ZA00741573A priority patent/ZA741573B/en
Priority to AU66702/74A priority patent/AU491734B2/en
Publication of GB1445592A publication Critical patent/GB1445592A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

1445592 Moulding plastic material INTERNATIONAL COMPUTERS Ltd 13 March 1974 [24 March 1973] 14288/73 Heading B5A [Also in Division H1] In a process of applying a layer of material having desired electrical properties to a substrate 1 with upstanding pillars 3, a predetermined quantity of resin containing solid particles in pellet form 8 is placed on the substrate and the assembly compressed between a block 4 and a heated ram plate 6, with the interposition of a release sheet 9 and an elastomeric sheet 7. The layer thus has a thickness equal to the pillar height. The layer may be electrically insulating and comprise an epoxy resin with magnesium silicate particles. The substrate may be copper for carrying an assemblage of integrated circuit elements and the pillars may be applied by electrolytic deposition. After applying the insulating layer, a multi-layer interconnected assembly of thin copper elements is produced, during which various insulating layers are compressed in the assembly in the manner described to encapsulate the conductive elements. The compressed material may be electrically conductive to provide film resistors.
GB1428873A 1973-03-24 1973-03-24 Insulated layers Expired GB1445592A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB1428873A GB1445592A (en) 1973-03-24 1973-03-24 Insulated layers
ZA00741573A ZA741573B (en) 1973-03-24 1974-03-11 Improvements in or relating to insulating layers
AU66702/74A AU491734B2 (en) 1973-03-24 1974-03-15 Improvements in or relating to insulating layers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1428873A GB1445592A (en) 1973-03-24 1973-03-24 Insulated layers

Publications (1)

Publication Number Publication Date
GB1445592A true GB1445592A (en) 1976-08-11

Family

ID=10038464

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1428873A Expired GB1445592A (en) 1973-03-24 1973-03-24 Insulated layers

Country Status (2)

Country Link
GB (1) GB1445592A (en)
ZA (1) ZA741573B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8604442B2 (en) 2006-07-20 2013-12-10 Gsi Helmholtzzentrum Fuer Schwerionenforschung Gmbh Method for determining the material composition of a material sample

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8604442B2 (en) 2006-07-20 2013-12-10 Gsi Helmholtzzentrum Fuer Schwerionenforschung Gmbh Method for determining the material composition of a material sample

Also Published As

Publication number Publication date
ZA741573B (en) 1975-02-26
AU6670274A (en) 1975-09-18

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Legal Events

Date Code Title Description
PS Patent sealed
PE20 Patent expired after termination of 20 years

Effective date: 19940312