GB1420794A - Error-correcting memory with partial write - Google Patents
Error-correcting memory with partial writeInfo
- Publication number
- GB1420794A GB1420794A GB5297173A GB5297173A GB1420794A GB 1420794 A GB1420794 A GB 1420794A GB 5297173 A GB5297173 A GB 5297173A GB 5297173 A GB5297173 A GB 5297173A GB 1420794 A GB1420794 A GB 1420794A
- Authority
- GB
- United Kingdom
- Prior art keywords
- error
- bytes
- bits
- check
- stored
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
- G06F11/1056—Updating check bits on partial write, i.e. read/modify/write
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Correction Of Errors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US00306779A US3814921A (en) | 1972-11-15 | 1972-11-15 | Apparatus and method for a memory partial-write of error correcting encoded data |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1420794A true GB1420794A (en) | 1976-01-14 |
Family
ID=23186802
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB5297173A Expired GB1420794A (en) | 1972-11-15 | 1973-11-15 | Error-correcting memory with partial write |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US3814921A (https=) |
| JP (1) | JPS5632719B2 (https=) |
| AU (1) | AU476372B2 (https=) |
| CA (1) | CA996277A (https=) |
| DE (1) | DE2357116A1 (https=) |
| FR (1) | FR2209468A5 (https=) |
| GB (1) | GB1420794A (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2136614A (en) * | 1980-06-25 | 1984-09-19 | Sundstrand Data Control | Recording digital date |
Families Citing this family (36)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2257213A5 (https=) * | 1973-12-04 | 1975-08-01 | Cii | |
| JPS5729797B2 (https=) * | 1975-01-16 | 1982-06-24 | ||
| US4005405A (en) * | 1975-05-07 | 1977-01-25 | Data General Corporation | Error detection and correction in data processing systems |
| GB1573329A (en) * | 1976-09-29 | 1980-08-20 | Honeywell Inf Systems | Method and apparatu for detecting errors in parity encoded data |
| US4072853A (en) * | 1976-09-29 | 1978-02-07 | Honeywell Information Systems Inc. | Apparatus and method for storing parity encoded data from a plurality of input/output sources |
| US4077565A (en) * | 1976-09-29 | 1978-03-07 | Honeywell Information Systems Inc. | Error detection and correction locator circuits |
| US4117458A (en) * | 1977-03-04 | 1978-09-26 | Grumman Aerospace Corporation | High speed double error correction plus triple error detection system |
| US4171765A (en) * | 1977-08-29 | 1979-10-23 | Data General Corporation | Error detection system |
| US4295219A (en) * | 1980-03-31 | 1981-10-13 | Bell Telephone Laboratories, Incorporated | Memory write error detection circuit |
| US4433388A (en) * | 1980-10-06 | 1984-02-21 | Ncr Corporation | Longitudinal parity |
| IT1202527B (it) * | 1987-02-12 | 1989-02-09 | Honeywell Inf Systems | Sistema di memoria e relativo apparato di rivelazione-correzione di errore |
| US4817095A (en) * | 1987-05-15 | 1989-03-28 | Digital Equipment Corporation | Byte write error code method and apparatus |
| JPH0821238B2 (ja) * | 1987-11-12 | 1996-03-04 | 三菱電機株式会社 | 半導体記憶装置 |
| US4884271A (en) * | 1987-12-28 | 1989-11-28 | International Business Machines Corporation | Error checking and correcting for read-modified-write operations |
| US4918695A (en) * | 1988-08-30 | 1990-04-17 | Unisys Corporation | Failure detection for partial write operations for memories |
| US5420983A (en) * | 1992-08-12 | 1995-05-30 | Digital Equipment Corporation | Method for merging memory blocks, fetching associated disk chunk, merging memory blocks with the disk chunk, and writing the merged data |
| US6047396A (en) * | 1992-10-14 | 2000-04-04 | Tm Patents, L.P. | Digital data storage system including phantom bit storage locations |
| US5675579A (en) * | 1992-12-17 | 1997-10-07 | Tandem Computers Incorporated | Method for verifying responses to messages using a barrier message |
| US6701480B1 (en) * | 2000-03-08 | 2004-03-02 | Rockwell Automation Technologies, Inc. | System and method for providing error check and correction in memory systems |
| FR2831970A1 (fr) * | 2001-11-02 | 2003-05-09 | Iroc Technologies | Procede de memorisation de donnees avec correction d'erreur |
| FR2831971A1 (fr) * | 2001-11-02 | 2003-05-09 | Iroc Technologies | Procede de memorisation de donnees avec correction d'erreur |
| US7051264B2 (en) * | 2001-11-14 | 2006-05-23 | Monolithic System Technology, Inc. | Error correcting memory and method of operating same |
| US7392456B2 (en) | 2004-11-23 | 2008-06-24 | Mosys, Inc. | Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory |
| WO2006057794A2 (en) * | 2004-11-23 | 2006-06-01 | Monolithic System Technology, Inc. | Transparent error correcting memory that supports partial-word write |
| EP2169555A4 (en) * | 2007-06-20 | 2011-01-05 | Fujitsu Ltd | CACHE CONTROL, CACHE CONTROL PROCEDURE AND CACHE CONTROL PROGRAM |
| JP4878606B2 (ja) * | 2008-04-01 | 2012-02-15 | エナジーサポート株式会社 | 消弧装置 |
| US7814300B2 (en) * | 2008-04-30 | 2010-10-12 | Freescale Semiconductor, Inc. | Configurable pipeline to process an operation at alternate pipeline stages depending on ECC/parity protection mode of memory access |
| US9251882B2 (en) | 2011-09-16 | 2016-02-02 | Avalanche Technology, Inc. | Magnetic random access memory with dynamic random access memory (DRAM)-like interface |
| US8751905B2 (en) | 2011-09-16 | 2014-06-10 | Avalanche Technology, Inc. | Memory with on-chip error correction |
| US9658780B2 (en) | 2011-09-16 | 2017-05-23 | Avalanche Technology, Inc. | Magnetic random access memory with dynamic random access memory (DRAM)-like interface |
| US20140344643A1 (en) * | 2013-05-14 | 2014-11-20 | John H. Hughes, Jr. | Hybrid memory protection method and apparatus |
| US9559726B2 (en) * | 2015-06-15 | 2017-01-31 | Intel Corporation | Use of error correcting code to carry additional data bits |
| US9766975B2 (en) | 2015-09-01 | 2017-09-19 | International Business Machines Corporation | Partial ECC handling for a byte-write capable register |
| US10176038B2 (en) * | 2015-09-01 | 2019-01-08 | International Business Machines Corporation | Partial ECC mechanism for a byte-write capable register |
| US9985655B2 (en) | 2015-09-01 | 2018-05-29 | International Business Machines Corporation | Generating ECC values for byte-write capable registers |
| KR102638790B1 (ko) * | 2016-09-13 | 2024-02-21 | 에스케이하이닉스 주식회사 | 반도체장치 및 반도체시스템 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3573728A (en) * | 1969-01-09 | 1971-04-06 | Ibm | Memory with error correction for partial store operation |
-
1972
- 1972-11-15 US US00306779A patent/US3814921A/en not_active Expired - Lifetime
-
1973
- 1973-08-09 CA CA178,459A patent/CA996277A/en not_active Expired
- 1973-08-22 AU AU59492/73A patent/AU476372B2/en not_active Expired
- 1973-09-06 JP JP9977373A patent/JPS5632719B2/ja not_active Expired
- 1973-11-14 FR FR7340537A patent/FR2209468A5/fr not_active Expired
- 1973-11-15 GB GB5297173A patent/GB1420794A/en not_active Expired
- 1973-11-15 DE DE2357116A patent/DE2357116A1/de not_active Ceased
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2136614A (en) * | 1980-06-25 | 1984-09-19 | Sundstrand Data Control | Recording digital date |
Also Published As
| Publication number | Publication date |
|---|---|
| AU476372B2 (en) | 1976-09-16 |
| US3814921A (en) | 1974-06-04 |
| DE2357116A1 (de) | 1974-05-22 |
| CA996277A (en) | 1976-08-31 |
| JPS4979737A (https=) | 1974-08-01 |
| JPS5632719B2 (https=) | 1981-07-29 |
| AU5949273A (en) | 1975-02-27 |
| FR2209468A5 (https=) | 1974-06-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PCNP | Patent ceased through non-payment of renewal fee |