GB2136614A

GB2136614A - Recording digital date

Info

Publication number: GB2136614A
Application number: GB8407988A
Authority: GB
Inventors: Paul H Eason; Jon B Groenewegen; Edward A Stephenson
Original assignee: Sundstrand Data Control Inc
Current assignee: Sundstrand Data Control Inc
Priority date: 1980-06-25
Filing date: 1981-06-16
Publication date: 1984-09-19
Also published as: GB2079516A; DE3124990A1; JPS5766550A; NL8103052A; FR2485780A1; GB8407988D0; GB2136614B; JPS6346890B2; GB2079516B

Abstract

A method for recording serial data in successive data blocks on a recording medium and verifying the accuracy of the recording is disclosed, together with apparatus for effecting the method. In the method, serial data received on line 26 is divided into blocks by temporary storage in BuFERA 61 or BuFERB 62 until the temporary store is full. A characteristic of the data block is stored in CHKSUM 60 and compared with a reference to determine the validity of the received data. A value related to that in CHKSUM is stored in CHEKIN 59. The data block is transmitted to transducer 33 and recorded on tape 30. A characteristic is stored in CHEKWR 63 and compared with CHEKIN 59 to verify the accuracy of the recording. The tape 30 is then rewound and the data block is read. A characteristic of the read data block is stored in CHEKRD 64. The values in CHEKWR, CHEKIN and CHEKRD are compared to verify the recorded data block. <IMAGE>

Description

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SPECIFICATION Digital data recording

5 This invention relates to a recording method and apparatus and more particularly to a method and apparatus for recording serial data in successive data blocks on a recording medium and verifying the accuracy of the recording.

The invention provides a method for recording serial data in successive data blocks on a recording medium, and verifying the accuracy of the recording, the method comprising receiving serial data, dividing 10 the received serial data into blocks, storing a characteristic of a data block, recording said data block, storing a characteristic of the read data block, and comparing the store characteristics to verify the recorded data block.

The invention further provides an apparatus for recording serialdata in blocks and for verifying the accuracy of recorded data, the apparatus comprising, means for dividing the serial data into data blocks, 15 means for detecting a characteristic of a data block, a first register connected with said detecting means to store said detected characteristic of the data block, a recording medium; means for recording said data block on said medium at a rate several times faster than the rate of said serial data, means for detecting a characteristic of the data block during recording, a second register for storing the characteristic of the recorded data block, means for reading the recorded block of data; means for detecting a characteristic of 20 the read data block and means for comparing the characteristics stored in each of the said registers to verify the recorded data block.

Theinvention is illustrated by the drawings, of which:

Figure 7 is a simplified block diagram of a recording system according to theinvention.

Figures 2 and 3 are velocity-displacement diagrams illustrating a method of employment of the recording 25 system of Figure 1;

Figure 4 is a diagrammatic illustration of a series of data blocks;

Figure 5 is a block diagram of an apparatus for practising the invention showing more detailthan in Figure

1;

Figure ffis a diagram showing the form of certain signals on the lines shown in Figure 5; and 30 Figures 7 to 15 are flow diagrams which illustrate a preferred mode of practising the invention.

The invention is disclosed herein as incorporated in a digital data recorder for aircraft, using a magnetic tape recording medium. The invention may be used in other applications and some aspects of it may be used with other recording media.

Referring particularly to Figure 1, digital and analog signalsfrom the aircraft are connected as inputs to a 35 flight data acquisition unit 25. The signals represent various parabieters of the aircraft operation which it is desired to record, as, for example, altitude, airspeed, pitch angle/control elements positions, engine parameters and the like. In the flight data acquisition unit, analog signals are converted to digital form and the various digital signals are time multiplexed to an output line 26 connected with a serial to parallel converter 27. The digital data is accumulated in storage register to form a data block, as will appear, and is 40 coupled to a parallel to serial data converter 28.

A magnetic recording tape 30 is movable between reels 31,32 past a magnetic read/write transducer 33. When a block of data is ready for recording, tape drive 34 is actuated to move tape 30 past transducer 33 and the serial data is coupled from the parallel to serial converter 28 through Write line 35 to transducer 33. The data is written on the tape at a substantially higher rate than it is received by serial to parallelconverter 27. 45 After the block of data is recorded, the tape drive is stopped. '

Turning now to Figures 2 and 3, movement of the tape will be described in more detail. Tape speed is plotted as a function of displacement. The tape starts from a standstill at 37 and accelerates until recording speed is reached at 38. The tape advances to point 39 when the data block 40 is written. The tape drive then decelerates and stops at point 42. The direction of movement of the tape is reversed and the tape accelerates 50 from the point 42 to point 43. The tape moves in the reverse direction to the point 44 and then decelerates to stop at point 45. The next block of data is written in a similar manner as shown in Figure 3. Tape movement starts from point 45 and the tape is accelerated in the forward direction to point 38'. Data block 40 passes the transducer 33 and at a prescribed position following data block 40, data block 40' is written. The tape drive is again decelerated to point 42' where it stops and reverses accelerating to point 43' moving to point 44' and 55 decelerating to stop at point 45'. The location of the next succeeding data block is shown in broken lines at 40'.

Speed of the tape may be selected to avoid the slip-stick problem and to minimize vibration induced flutter, without regard to the rate of data acquisition. Further, reasonable acceleration and deceleration rates may be used and the space between successive data blocks (interrecord gap or IRG) minimized for efficient 60 use of the tape.

It will be noted that the data block 40 passes transducer 33 during movement of the tape in the reverse direction between points 43' and 44'. Stopping point 45 is selected so that point 38' is ahead of the leading edge of data block 40 on the successive recording cycle so that data block 40 passes the transducer 33 in the forward direction before data block 4TTs recorded. During one of the passes of data block 40 past transducer 65 33, the recorded information maybe read and verified by comparison with the data recorded. Referring

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again to Figure 1, comparator 49 has an input connected with Write line 35 and another input connected with read line 50. If the data which had been written on the tape does not agree with that which was read from the tape, an error signal is given.

A playback control 52 is connected with tape drive 34 to move the tape continuously for reading the 5 recorded data. This is preferably carried out at the same velocity at which the data was recorded. A switch 53 is actuated by playback control 52 to couple the recorded signals from read line 50 to an output from which they may be copied or otherwise utilized.

In one embodiment of the invention the data blocks have a length LD of 0.42 inch and an interrecord gap of 0.06 inch. This provides a record density of 87.5%. See Figures 3 and 4. Morever, it should be noted that 10 dimension of the interrecord gap is independent of tape speed.

In the embodiment of the invention illustrated herein, the tape speed during recording (and during tape reversal) is six inches per second. The average tape speed, however, is only 0.48 ips. The continuous serial data from the flight data acquisition unit has a rate of 768 bits per second (BPS). Data is accumulated for one second and a block of 768 bits is recorded at a rate of 11.2 K BPS. The recorded data can be copied in a 15 fraction of the time that it was recorded by running the tape continuously. Typically, several tracks of data will be recorded sequentially on a single tape. All of the tracks can be copied simultaneously minimizing the time that the recorder is not available for use on aircraft.

The recorder is preferably controlled by a programed microprocessor. Figure 5 illustrates diagrammatical-ly the functional interconnection of a data source and read/write transducer 33 with buffer registers 55,56 20 and 57, central processor unit (CPU) 58 and storage registers 59-64 provided by a RAM register. The circled numerals in Figure 5 represent the sequence of events during the receipt, recording and verification of one block of data, as will be described below.

Registers 55,56 form a programable communications interface (PCI) providing synchronous receiver and transmitter sections. The receiver couples the data from flight data acquisition unit 25 to CPU 58 and the 25 RAM registers while transmitter 56 couples data from the registers and CPU to the transducers 33. Register 57, which is part of the system timing controller (STC) couples data to the CPU and registers 63,64 for verification of the recording, as will appear.

The data online 26 from the flight data acquisition unit, step ©, is in continuous biphase form at a rate of 768 BPS, see Figure 6A. Biphase demodulator 66 converts the data to NRZ (nonreturn to zero) format with a 30 clock or strobe signal, step©, as shown in Figure 6B. The data and strobe signals are connected with receiver buffer 55 which groups the serial data in eight bit bytes which are transmitted in parallel form to CPU 58 to step ©. Buffer 55 is shown as a single element for simplicity. In practice, it is two stages wide so that serial incoming data is not interrupted or lost while a byte of data is transmitted to CPU 58. Similarly, buffers 56 and 57 are preferably two stages wide.

35 RAM registers 61,62 are designated BUFERAand BUFERB. Each has a capacity of 96 bytes. The received data is collected in one of the registers, as BUFERA, until 96 bytes or 768 bits has been stored, step @ . This is the data received in one second. Then, as will appear, the data in the filled buffer register is transmitted for recording while incoming data is stored in the other BUFERB

In the CPU a preamble and postamble are added to the data block to aid in identification in later analysis of 40 the data. Each is composed of seven 0's and a 1.

RAM register 60, designated CHKSUM, has a two byte capacity and receives information characterizing the received data, step © . More particularly, the CHKSUM figure is 787 plus the sum of the one bits occurring in the one second block of received data. 787 is the number of polarity reversals for 768 bits of 0 data with the preamble and postamble. The CHKSUM is compared with a reference to determine thevalidity of the 45 received data. At step© a figure representing CHKSUM divided by two is stored in CHEKIN register 50 for later use in verifying the recorded information.

When BUFERA is filled, the recording operation is initiated. At the same time, incoming data is directed to BUFERB. The received data in BUFERA, together with a preamble and postamble, are directed to transmitter buffer 56, step ©. The eight bits of each byte are coupled simultaneously to the register and then strobed 50 out of the register at the rate of 11.2 KBPS, step®. The serial data from buffer 56, which has an NRZ format, is connected with biphase modulator 67 which has an output, step©, which is biphase inform at the 11.2 KBPS rate. When BUFERA is empty, all of the data has been transmitted, completing the formation of the data block to be recorded.

The signal at line 68, shown at Figure 6C, is a short block of data in which the data bits have a biphase 55 format, corresponding with one second of received data plus the preamble and postamble. This signal is coupled through Write amplifier 69 to transducer 33 and is recorded on the tape 30. During the Write operation switch 72 is in the WR position and the signal on line 68 is coupled through line 73 and eight stage register 57 to the CPU, steps ©, © and ©. The positive transitions of the data are counted and the number stored in CHEKWR register 63, step©. CHEKWR is compared with CHEKIN to verify the accuracy of 60 the recorded data.

During reading of the previously written data block, described above in connection with Figure 3, switch 72 is connected in the RD position, step© . The recorded data which is read by transducer 33, Figure 6D, is coupled through Read amplifier 75, switch 72 and line 73 to register 57, step©. The output of the register is connected with CPU 58, step©, and a figure representing the positive signal transitions is directed to 65 CHEKRD register 64, step © . This figure is compared with CHEKWR from register 63 and CHEKIN from

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register 59 to verify the recording and playback of the data signal.

The operation of the data recorder will be further explained with reference to the functional flow diagrams of Figures 7-15.

In Figure 7, overall operation is summarized. Operation starts with a reset of the system when the power is 5 turned on, step 80. The system is initialized at 81. An operating mode determination is made at step 82. If the system is in standby, the program returns to initialize, step 81. In the flight record mode, the flight record controls are initialized at step 83. Serial data from the flight data acquisition unit is received and directed to BUFERA or BUFERB at 84. So long as 768 data bits have not been received, the data is directed to the buffer, step 85. When 768 data bits are received, the program moves to step 86. The received data is directed to the 10 other RAM buffer. The tape is moved in a forward direction, the previous data block is verified and the data in the filled buffer is written on the tape. At step 87 if the end of the tape is not detected, the received data continues to storage in the RAM buffer and the reverse tape motion is effected as described in connection with Figures 1,2 and 3, step 88. At step 89 a check is made for a standby mode command. In its absence the program returns to step 84 and repeats. If there is a standby command, the program returns to step 81. 15 In the event an end of tape condition is found at step 87, the program proceeds to step 90 which increments the track selection to move to the next track of a multi-track tape and erases a sufficient length of the tape to eliminate old data and permit the recording of the next data block.

At step 82 the external equipment mode selection provides for various operations which may be used in examining the recorded data, copying it to another tape or to an external computer or the like. These 20 functions are not a part of the present invention and will not be described in detail herein. At step 92 the external equipment controls for the selected mode or submode are initialized. The modes indicatd include:

a. rewind to beginning of tape b. forward to end of tape

25 c. run continuous, normal direction d. run continuous, antinormal direction.

At step 93 the operations for the selected submode include controlling tape motion; controlling read/write operation; and changing tape track as required. At step 94, determination is made whether the mode or 30 submode has been completed. If it has not, the operation continues as determined at step 93. If the mode has been completed, the program returns to step 81.

Figure 8 is a simplified flow diagram for the flight record mode of operation FLTREC. It provides an outline for the functions which will be described in further detail in connection with Figures 9-15. Upon entry into the FLTREC operation, RDSET step 96 selects the RAM buffer in which received data is to be stored and initializes 35 other circuits. When a block of data has been assembled, it is recorded at FSTROK-97. Following recording a determination is made whether the end of the tape has been reached (and this is the usual condition), tape backup or check stroke (CSTROK) is initiated at 99. The program then continues to RDWAIT step 100 until a full buffer of data is accumulated. In the event the end of tape was identified at step 98, the CSTROK step 99 is omitted at 101 and a track change effected by another program, not shown.

40 Further detail of the flight record function, FLTREC, is illustrated in the flow chart of Figure 9. The PCI receiver 55 is cleared and initialized at step 105. An erase control is enabled at step 106 to erase the tape of old data before a new data block is recorded. At step 107 a check is made to determine whether a Write operation is currently in progress. If a Write is not in progress, the assignments of BUFERA and BUFERB are switched or toggled at step 108 and the program proceeds to the RDSET submoduleat 109. This will be 45 further described in connection with Figure 10. If a Write is in progress at step 107, step 108 is omitted and the program proceeds to step 109.

At step 110 a forward stroke, FSTROK, is initiated and the previously written data block is verified. This will be further described in connection with Figure 11. Step 111 corresponds with step 98 of Figure 8, checking for an end of tape signal. If no track change is required at step 112, the program proceeds to step 113 at 50 which the tape direction is reversed. Further details will be given in Figure 12. If a track change is required, step 113 is bypassed. At step 114 a check is made for standby operating mode. In its absence the program proceeds to step 115 RDWAIT, to be further described in Figure 13, and returns to step 108 when the next block of data has been received by PCI receiver 55.

The functions performed during the RDSET submodule in setting up the assignments for BUFERA/BUFERB 55 are illustrated in Figure 10. At step 118 a check is made to determine whether BUFERA is the designated receiver buffer. At steps 119,120 the address of the appropriate buffer is stored in a RAM register (not shown) to indicate to which buffer received data should be directed for storage. At step 121 CHECKSUM register 60 is cleared and set to the initial figure of 787 in preparation for receiving characterizing information regarding the incoming data. At step 122 a byte is cleared from the filled RAM buffer to PCI transmitter 56 60 and a loop 123 is executed until all bytes have been cleared. This completes the RDSET submoduie and control is returned to the FLTREC program.

The FSTROK submodule 110 is illustrated in Figure 11. This program executes the steps which initialize the system in preparation for the Write operation, verify the preceding recorded data block and record the data from the filled one of buffers A/B 61,62. At step 126 a check is made to determine which buffer is filled and 65 selected for writing data to the tape. The appropriate buffer pointer is set and stored at step 127. A check is

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then made at step 128 to determine the track number in use on the tape and thus the direction of motion of the tape for recording. The appropriate motor control flag is stored at step 129. At step 130 the tape drive motor is started and accelerated to the speed used for reading and for writing.

The tape drive motor is a multi-phase, bidirectional step motor. A count of the motor steps affords an 5 accurate measure of tape speed during acceleration and deceleration and of tape position.

At step 131, playback of the previously recorded data is intiated and continued until the motor step count indicates that the interrecord gap has reached transducer 33. At step 133 playback is disabled and the signal characterizing the playback data is stored in CHKRD register 64. At step 134 the data characterizing information in the CHKIN and CHEKWR registers 59,63, respectively, are compared. If they agree, the data 10 process fault register (not shown) is cleared at 135. If they disagree, a count is added to the fault register at 136. At step 137, the data characterizing information in the CHEKRD register 64 is compared with that in CHEKWR register 63. If they agree, a zero is shifted in to theCHEKER register (not shown); and if they disagree, a one is shifted into the CHEKER register and a data check fault output signal is generated. At step 140 a determination is made whether the CHEKER register shows eight successive faults. If it does not, the M 15 fault register is cleared at 141. However, if there have been eight successive faults, this is recorded in the M fault register at 142.

Motor step counter 145 determines when the end of the interrecord gap is reached. At step 146 PCI data transmitter 56 is actuated and Write current is delivered to the transducer 33. Motor step counter 147 identifies the end of the data block. The transmission of data from PCI transmitter 56 is terminated at step 20 148. The motor drive is stopped step 149 and the Write head current disabled at 150. The data is CHEKWR register 63 is saved.

The program illustrated in Figure 12 provides for the reverse motion of the tape and is designated CSTROK. At steps 155,156 the track number is determined and the correct motor direction control flag is set. The appropriate flag is stored at step 157. The motor is started and accelerated at step 158. The motor steps 25 are counted at 159 and the motor decelerated and stopped at 160 when the appropriate count is reached.

This positions the tape at point 45, Figure 2, in readiness for the next FSTROK operation. Figure 11.

Figure 13 illustrates the program for the RDWAIT submodule, element 115 of Figure 9. At step 163 a data loss counter is initialized. If this counter should time out before a full buffer of data is received, a fault condition is established. Following initialization of the counter, the program monitors the received buffer 55 30 and the counter at steps 164,165. If the receive buffer fills before the data loss counter overflows, the recorder status fault is set to zero at step 166 and the CHEKSUM is examined at steps 167,168 to insure that it is between the limits of 787 and 1555. If the CHEKSUM is correct, the data process fault flag is cleared at step 169 and at step 170 the CHEKSUM data is moved to CHEKIN register 59. If the CHEKSUM is outside its limits, a fault flag is set at step 171. In the event the data loss counter overflows, a fault flag is set at step 172. 35 Figure 14 illustrates the program for submodule RXRDY which is performed as an interrupt procedure to transfer the received aircraft data from PCI register 55 to the designated one of BUFERA/BUFERB and to perform other related functions. At step 175 the data is moved from the PCI register to the RAM buffer as selected at steps 119,120, Figure 10. For each byte of 8 bit data which is transferred to the buffer, a procedure is followed to generate the CHEKSUM. At step 176 a register (not shown) is set to 8, corresponding with the 8 40 bits of data. At steps 177,178 the CHEKSUM is incremented for each one bit in the received data. At step 179 the register is decremented as each data bit is examined. When the register reaches zero at step 180, the CHEKSUM is stored at step 181. At step 182 the condition of the receiving buffer is examined. If it is not full, the buffer pointer is incremented at 183. When the buffer is filled an appropriate status flat is set at step 184.

Submodule TXRDY, another interrupt process, is illustrated in Figure 15. This program is involved in the 45 transfer of data to be written on the tape from the buffer to the register of the PCI transmitter 56. A byte counter (not shown) is incremented at 188. This counter records the number of bytes which have been transferred from the buffer to the data transmitter. If the count is less than 97 at step 189, step 190 sends the next data byte to the data register of the PCI transmitter 56. When 97 bytes have been transmitted (96 data bytes preceded by the preamble) this count is identified at step 191 and the postamble is sent to the PCI 50 register at step 192. When the count exceeds 97 the TXRDY interrupt is disabled at step 193 and the Write operation is terminated.

The foregoing specific simplified programs are given to illustrate the general operation of a data recorder utilizing the invention. Many of the detailed procedures and tests desirable for a commercial product are not shown as they are not a part of the invention and their inclusion would unnecessarily complicate the 55 disclosure.

Further aspects of the data recorder, particularly related to the acquisition of data and to the procedure for playback or copying are disclosed in our applications No. 8118414 and 8118416, from the latter of which this Application is divided.

Claims

60 CLAIMS

1. A method for recording serial data in successive data blocks on a recording medium, and verifying the accuracy of the recording, the method comprising receiving serial data, dividing the received serial data into blocks, storing a characteristic of a data block, recording said data block, storing a characteristic of the read 65 data block, and comparing the store characteristics to verify the recorded data block.

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2. A method according to claim 1 further comprising comparing the first store characteristic with a standard.

3. An apparatus for recording serial data in blocks and for verifying the accuracy of recorded data, the apparatus comprising, means for dividing the serial data into data blocks, means for detecting a

5 characteristic of a data block, a first register connected with said detecting means to store said detected 5

characteristic of the data block, a recording medium; means for recording said data block on said medium at a rate several times faster than the rate of said serial data, means for detecting a characteristic of the data block during recording, a second register for storing the characteristic of the recorded data block, means for reading the recorded block of data; means for detecting a characteristic of the read data block and means for 10 comparing the characteristics stored in each of the said registers to verify the recorded data block. 10

4. An apparatus according to claim 3 further comprising means for comparing the stored characteristic in said first register with a standard.

5. A method according to claim 1, the method being substantially as described herein with reference to the drawings.

15 6. An apparatus according to claim 3, the apparatus being substantially as described herein with 15

reference to the drawings.

Printed in the UK for HMSO, D8818935, 7/84, 7102.

Published by The Patent Office, 25 Southampton Buildings, London, WC2A 1AY, from which copies may be obtained.