GB1490206A - High-reliability digital data read/write system for magnetic tape in cassettes - Google Patents

Abstract

1490206 Writing and reading digital data FRANCE MINISTRY OF POST & TELECOMMUNICATIONS and COMPTEURS SCHLUMBERGER 17 Oct 1974 [19 Oct 1973 11 Oct 1974] 45018/74 Heading G4C In a device for writing and reading digital data blocks on and from magnetic tape cassettes 11, 12, each data block being in the form of characters having 8 data bits completed by a parity bit, each character is written serially twice consecutively, and a preamble character, 010101011, is written at the head of each block twice consecutively. Writing.-Digital data is delivered in parallel from a source 100 to a buffer register 5 by timing signals from a write timebase 2, the data and a parity bit generated therefrom by a generator 6 passing to a parallel-serial converter 7. Timing signals from the write timebase 2 cause the data from parallel-serial converter 7 and the preamble from a shift register 8 to pass via an OR gate 9 to a phase modulator-coder 10 whence the coded characters are written on whichever of cassettes 11, 12 is chosen by a routing circuit 13. Reading.-Characters from one of the cassettes 11, 12 are decoded in a phase demodulatordecoder 14, the decoded characters passing via a serial-parallel converter 15 to a preamble detector 40, a synchronization and release circuit 4, and buffer registers 21, 22. Should one or both preamble characters be detected by the preamble detector 40, signals are sent to the synchronization and release circuit 4 and to a read timebase 3 which initiate a true or false character sort circuit 20. In operation of the sort circuit 20, a character and its repeated character are read into the buffer registers 22, 21, respectively, their parity codes being checked by code verification circuits 26, 25, respectively, and the characters also being compared bit-by-bit in a comparator 27. If both even parity codes are true, the first character is gated out of buffer register 22 to a utilization circuit 16 by means of a selection circuit 23. If only one parity code is true, the character of true parity is gated out. If both parity codes are false and the characters are not identical bit-by-bit, the repeated character is gated out, and an error signal is produced which lights a lamp 28. In operation of the synchronization and release circuit 4, the preamble characters (of 9 bits in length or 1 cycle of the read timebase 3) are searched for during a period of 22 bits (or about 2¢ cycles). If preamble character(s) are sensed by the detector 40, signal(s) 51 are sent to the circuit 4, which synchronizes the characters by means of the preamble(s) and in turn sends a signal 55 to the read timebase 3. The latter then initiates the sort circuit 20 before the arrival of a first data character read signal 52 (at the end of the fourth cycle).