DE2449715A1 - ARRANGEMENT FOR WRITING AND READING NUMERICAL INFORMATION BLOCKS ON OR FROM A CASSETTE MAGNETIC TAPE - Google Patents

Description

description
to the patent application

of the French State - CENTER NATIONAL D ¹ ETUDES DES TEIECOMMUNICATIONS, 38-4o avenue du General Leclerc, Issy les Moulineaux / France

and the company SCHLUMBERGER INSTRUMENTS ET SYSTEMES, 42 rue Saint-Dominique, Paris 7 / France

concerning:

"Arrangement for writing and reading out numerical information blocks on or from a magnetic cassette tape"

The invention relates to an arrangement for registering and restoring numerical information on magnetic cassette tape and in particular an arrangement of the type in which the information is written and read is in drawing pads.

Magnetic cassette tapes can be used as peripheral units for computing systems or process control systems will. In particular, they can serve as a large-capacity buffer for registration

509824/0802

2A49715

and restitution of programs, as memory, and read-only memory for accounting quantities, such as prices, taxes, etc. or for statistical quantities as excess storage in the event the saturation or in the event of a main memory failure, etc.

Numerical recording on magnetic tapes is well known. The width of the magnetic tape is generally from 5, 81 mm, which requires a recording in series of bits. Two methods of recording are used, namely recording on a single track with phase encoding or recording on two tracks in NRZI complementary mode. In the latter case, it should be specified that recording on two tracks does not mean duplication of information, but only a technical necessity due to the NRZI code used. One or the other method gives rise to serious security problems in order to achieve flexible application and high security, in particular in systems that are connected to industrial processes, in which there is no possibility of correcting an error by the program.

The arrangements for writing in and reading out on or from cassette magnetic tapes are particularly marked due to their simplicity and the low prime costs. Resulting from the simplicity of the components used disadvantages that lead to malfunctions in the functions of writing and reading on the magnetic tape and can bring mistakes. The main causes of such disorders include:

Low mechanical tension in the tape on the surface of the read / write head. Mechanical

- 3 50982W0802

Vibrations to which the belt is subjected during its movement lead to a bad one Deletion of the information that was previously registered. In the previously usual arrangements is ee required to first pass the tape through an external one Organ to be deleted or by a roll-off process before re-enrolling. This leads to a serious limitation of applicability;

the low resistance to mechanical and magnetic wear of the tape due to its low thickness of 2o / u , which quickly leads to localized defects.

the fact that the tape reaches its target speed only after a transition period during which the speed is not constant.

The object of the present invention is to provide an arrangement for writing in and reading out numerical information blocks to create on or from a cassette magnetic tape, in which the restitution errors as a result the relative robustness of the magnetic tape cassettes can be corrected.

In systems for transmitting quantities, it is known to transmit words or characters twice in succession. The errors are detected by comparing the two received characters bit by bit. It is also known to groups of bits that make up a character, a parity check bit to add. A parity check bit is a bit that is appended to an encoded group in such a way that the sum of the Bits of a given value, for example 'of a bit,

- 4 -509824/0802

2A49715

is even or odd, depending on whether one a parity check or an imparity check performs. The invention uses the known method, which consists in converting the characters into "true" characters and "wrong" characters are sorted by repeating each character and the parity of the code of the two received characters is verified and they are compared with each other bit by bit.

The information registered on the cassette tape is mainly intended to be read intermittently in whole blocks so as to be transmitted or to serve as a process control variable. The cassette is therefore not, as in the usual application, a set in motion once and for all to enable all the information contained to be played back once and for all, on the contrary, it is intended to be subjected to a sequence of starting and stopping operations in order to to enable reading of blocks of information one after the other or in groups, whichever one only a few blocks included. The problem of the synchronization of the characters arises accordingly for everyone Startup of the cassette and it is necessary to ensure that this synchronization is carried out correctly, before proceeding to the actual reading of the information.

According to the invention, the information blocks are preceded by a preamble character which, like the characters of the Is written twice in succession on the magnetic tape. This preamble is not a sign of information of the block intended to be read; it is simply a function character with the

509824/0802

same number of bits as the information character. The arrangement for writing and reading the cassette magnetic tape comprises circuitry for decoding the characters, circuitry for controlling the character sorting process into true and false characters, a circuit for counting a certain number of bits, starting from the reception at the beginning of the first preamble, so that a preamble search period is defined with a duration at least equal to the duration of the two characters (this duration hereinafter referred to as "cycle") circuitry for detecting the preamble in this preamble search period and for generating an additional two reception pulses of the preamble, if the preamble and its repetition are correct circuitry for synchronizing the decoding circuitry for the characters by these preamble pulses and circuitry for unlocking the sorting control circuit for the characters if at least one preamble reception imguaä has been generated within the mentioned preamble search period.

In the following it is assumed that the words are octets of eight bits but contain nine bits under consideration of the parity bit. Nonetheless, the words should be referred to as octets.

The writing on the magnetic tape is done by phase coding. It is well known that this enrollment process the bits represented by transitions, and certain transitions are in the middle of bits when two bits of the same value follow one another. Accordingly, one can say that there are distinctive transitions and there are not distinctive transitions. The latter are eliminated by the phase decoding circuit, but if one is not significant transition is not eliminated by the de-

E09824 / 0802

2449718

coding circuit, this leads to a decoding error. One can therefore choose, according to the invention, between a preamble which is inconsistent with the Parity bit only contains true transitions because it does not contain any bits of the same value consecutively except at the end. This preamble is as follows:

ololololl

A summary of the main features of the invention emerges from the attached claim 1, while further advantageous features emerge from the subclaims and the following description of an exemplary embodiment result.

The invention is explained in detail below with reference to the accompanying drawings.

Fig. 1 shows in the form of a block diagram the arrangement for writing and Reading onto or from a cassette magnetic tape according to the invention,

Figs. 2 and 3 are signal diagrams for explanation the phase coding,

Fig. 4 shows in detail the synchronization circuitry for the character decoder and the unlock circuit for the character sorting control circuit, and

- 7 4/0802

Fig. 5 is a signal diagram for explanation the circuits of FIG. 4.

In Fig. 1 a pulse generator 1 can be seen, which supplies pulses with a frequency of 6 MHz, for example, to a write-in time base 2 and to a read-out time base 3. This read-out time base is assigned to a synchronizing and unlocking circuit arrangement and comprises two parts, an actual time base J> o and a programmer Jl. The actual time base j5o supplies the demodulation phase decoder 14 with the signals k ^f and k ^M as clock signals which are required for the demodulation. The time base works as soon as the arrangement is switched _{to the reading position 3} to enable the preamble to be read. The sorting control circuit for the characters or programmer Jl only works when the synchronizing and unlocking circuit

4 has unlocked it. It follows that the preamble must be received at least once within the preamble search period, so that the characters are really sorted.

With the reference character loo, a source is numerical Signals which are located outside the arrangement according to the invention and which are connected to a buffer register 5 that belongs to the arrangement according to the invention, so that characters parallel to it in the form of Octets with eight bits are supplied. The buffer register

5 is assigned to a parity bit generator 6. The buffer register 5 and the parity bit generator 6 are connected in parallel to a shift register 7 which operates as a parallel serial converter. The shift register 8 contains the preamble. The shift registers <f and 8 are connected to a modulation phase encoder Io by means of an OR gate 9.

509824/0802

Pie transmission delay between the buffer register 5 and the parity bit generator 6 on the one hand and the shift register 7 on the other hand takes place in such a way that in the Register 7 the octet of nine bits is written. The enrollment time base 2 effects this transmission twice, to cause the octet to be written to be doubled.

The phase coding modulator Io is of known type. It comprises two AND gates Iol and Io2 and a trigger circuit Io3, which are connected as a binary multiplier. The information bits (Fig. 2, line a) reach the two AND gates, directly to the AND gate lol and via an inverter Io4 to the gate Io2. The clock signal h ^f (Fig. 2, line b), which comes from the write-in time base and consists of pulses that are in the middle of bit intervals, is applied to the gates lol and Io2, and the clock signal h ^M (Fig. 2, line c), which also comes from the write-in time base and consists of pulses that are at the limits of the bit intervals, is applied to the "isolating input" of the flip-flop Io3. If a zero is received when the trigger circuit loj is in the switching state zero, it is inverted by the inverter Io4 and the gate Io2 is opened by the pulse h ^f . The switching state zero of the multivibrator is confirmed; this is then brought into switching state one by the following pulse h ^ff . When the first one is received, the gate lol is opened at the moment of the pulse h ', which confirms the trigger stage loj in the sound state one. With the next pulse h ^tf , the flip-flop is brought into the switching state zero. When the second one is received, the AND gate lol is opened at the moment of the pulse h ', whereby the flip-flop from the switching state zero into the switching

509824/0802

brought to state one. The flip-flop is brought into the switching state zero with the next pulse h ^lf. It can be seen that the pulse h ^M always causes a change in polarity, while the pulse h ^r only causes a change in polarity if the polarity of the information bit has not changed. Finally, the signal of line d of FIG. 2 is obtained, which is applied to the write head of one or the other of the cassettes 11 and 12 via a selection circuit 13. In FIG. 2, line d are the significant transitions of the signal corresponding to the beginning and the end of a bit is marked by an arrow, while the insignificant transitions corresponding to the middle of a bit, if the previous bit had the same value, are not marked with arrows.

The write-in time base 2 controls the various write-in circuits, in particular the output of the characters from the numerical information source loo, the input and output of the words in buffer register 5, the progression the shift registers 7 and 8 and the phase encoding modulator lo.

The reading section includes the phase decoding demodulator 14, the input of which is connected to the reading heads of the cassettes 11 and 12 via the selection circuit I3. The exit of the demodulator 14 is connected to a shift register 15 which serves as a series-parallel converter. The shift register is connected in parallel with the character sorting circuit (sorting into true and false characters) 2o, the one first buffer register 21, which in turn is connected to a second retrieval register 22. These buffer registers 21 and 22 are connected to a processing circuit 16 via a selection circuit 23 and an interface 24.

. The buffer registers 21 and 22 are each assigned to one of two code verification circuits 25 and 26, respectively and on the other hand a bit-by-bit comparator 27. The output

509824/0802

-Io -

- Io -

gears of circuits 25, 26 and 27 are connected to the voting circuit 23. The voting circuit transmits to utilization circuit 16:

The first octet if the parity codes of the two octets are both exact;

the octet whose imparity code is exact if the parity code of an octet is exact and that of the other octet wrong;

the second octet and an error signal if the parity codes of both octets are wrong and if the content of the octets is not identical bit for bit. The error signal causes a lamp 28 to light up.

The V-ahlschaitkreis 2j5 contains the necessary gates for realizing the selection criteria just explained. Since the downstream buffer register 22 successively contains the original octet and the repetition octet, these gates are opened at the right moment in order to transfer the desired octet to the circuit 16. Selector circuit ( 27) type circuits are known in the art. For example, reference can be made to US Pat. No. 2,892,888 which describes a selection circuit for selecting between two words which are received and which correspond to the same word originally sent on two different transmission channels, according to a criterion which is the same Comparison conditions bit by bit and the code verification includes, as described above, with additional conditions regarding the noise level on the transmission

- 11 -

509824/0802

24 * 9715

channels. These latter conditions do not form the subject of the present invention, which contrary deals with a problem of reading sizes from a magnetic tape, rather than a problem the transfer of sizes.

The phase decoding demudulator 14 is of known type. It comprises a signal shaping circuit for the signal read out (not shown), such as a Schmitt trigger, two AND gates 141 and 142 and a bistable multivibrator I4j5. After shaping (FIG. 3, line b), the information bits are applied to the two AND gates, directly to AND gate 142 and via an inverter 144 to AND gate 141. The clock signal k ^f (FIG. 3, line c), which comes from the readout time base via connection 146 and consists of pulses that are located at the interval limits of the bits and the signal k ' ^f (FIG. 3, line d), which also comes from the readout time base via connection 147 and consisting of peaks centered on the middle of the bit intervals are applied to AND gates 141 and 142, the first as an enable signal and the second as a disable signal. The peaks k ¹ ′ suppress the insignificant transitions of the phase modulation which are therefore not applied to the flip-flop 143. A pulse is generated by the flip-flop 143 every time the logic state of the information bits changes. Finally, the signal along line e in FIG. 3 is obtained, which is a signal NRZ.

The demodulator 14 is connected to the reading time base 3 via the connection 145, with which the bit synchronization is ensured.

The reading time base 3o comprises a frequency divider -3ol, the pulses from the pulse generator 1 with 6 MHz

- 12 -

509824/0802

and dividing the frequency by 128 to provide clock pulses with a bit frequency of 47 kHz. The frequency divider J5ol is connected to a second frequency divider J5o2, which divides the input signal frequency by 9 and to which a decoder J5o3 is assigned. The decoder J5oj5 supplies clock signals to nine outputs without resetting to zero and in groups of nine, T ₁ to Tq. The signals.T ₁ to Tq correspond to the bits of a character to be read.

The synchronizing and unlocking circuit 4 receives the signals Th and Tj- from the decoder J> o3, the end of the block signal from register 15, the preamble decoding signal 51 from register 4o and the ringing signal of the first character 52 from the programmer. The synchronizing and unlocking circuit has two functions; it synchronizes the characters using the preamble and unlocks the programmer.

The symbol synchronization circuit comprises the flip-flops 4ol, 4o2, 4o4 and 4o5 as well as the NAND gate 4o3. The trigger stage 4ol is in the switching state One brought by the signal T, - and into the switching state Zero by the signal T ^ (Fig. 5, line a).

The output Φ of the flip-flop 4ol is connected to the flip-flop 4o2, which comes into the switching state one with the first negative pulse (positive to Q) of the flip-flop 4ol (Fig. 5, line b). The flip-flop 4o4 goes to the switching state one when 4o2 is in the switching state one, the synchronization circuit receives the signal T ₅ (Fig. 5, line c), and the flip-flop 4o5 goes into the switching state one when step 4o4 flips (Fig. 5 » Line d). Coming from the switching state one, the flip-flop 4o5 determines the end of a period of

- 13 -

509824/0802

twenty-two bits, which is the preamble search period acts. Those skilled in the art will recognize that the circuits 4öl to 4o5 play the role of a counter / which counts to 3 and which has the task of detecting the third signal Tj-, starting from the beginning of the block.

The output signal of the flip-flop 4o5 and the Decoding signals of preamble 51 are applied to the NOT-AND gate 4o6. At the output of this gate one receives the signal 54 for the character synchronization, the is applied to the frequency divider J5 ° 2.

The signal 51 of the preamble decoding (Fig. 5, line e), which appears either in the first cycle of the time base 3 alone or in the second cycle of this time base or in both cycles, puts the flip-flop 4o7 in the switching state one (Fig. 5, Line g). The call signal 52 of the first read character sets the flip-flop 408 to the switching state zero (Fig. 5t, line h). If at the same time 4o7 is in the switching state one and 4o8 is in the switching state zero, the gate 4o9 is open and the flip-flop 4lo is brought into the switching state one. The flip-flop 41 o accordingly defines a period between the first or the second preamble decoding signal and the ringing signal of the first character read. The signal from the output of the flip-flops 4o5 and 41o is applied to the inputs of a NOT-ANDr'Gate 411, which is unlocked at the moment 55, if this moment is after the detection of at least one preamble and before the arrival of the first information character at the interface of the Exit of the arrangement. The signal 52 that the arrival of the first

- 14 -

509824/0802

Information sign marked on the interface 24 is a short signal which coincides with the end of the timer signal Tq of the fourth cycle. Because you need two cycles for acquiring the preamble (s) and two more cycles for receiving and processing the first information character and its duplicate. That means that at the end of the fourth cycle the first character if the code verification and the identity of each bit were correct, is located at the input of the interface.

It can be seen that, if at least one preamble has been correctly received during the preamble search period, two effects occur: The signal 54, which is nothing other than one or the other of the two signals 51 , causes the symbols to be synchronized by acting on the frequency divider J > o2: the signal 55 unlocks the programmer, thus ensuring the functioning of the parity verification circuits, the comparator and the selection circuit. However, if no preamble has been correctly received during the preamble search period, there is no synchronization of the characters and no unlocking of the programmer. The programmer is not unlocked before the occurrence of the signal 52, and thus the first information character is not transmitted to the interface either.

The selection circuit 13 is controlled by the Pushbutton switches Ij51 and 1 ^ 2 to switch one or the other of the choose the two cassettes 11 and 12 respectively. Furthermore, each tape has a warning signal 40 cm before the actual end of the tape that is read out by a photoelectric cell. A signal is also transmitted through the lines 111 or 121 to the programmer Jl, who at the end of the

509824/0802

Carrying the last block automatically energizes the selection circuit 1J> without change or modification between the last block of the cassette 11 and the first block of the cassette 12 or inversely as far as the cassettes are concerned.

Patent claims:

- 16 -

509824/0802

Claims (4)

- claims IJ arrangement for writing and reading out ^ / numerical information blocks on or from a magnetic cassette tape, which blocks are in the form of characters with a certain number of bits, completed by a parity bit, with circuits for writing each character serially in two-fold succession, Circuits for writing at the head of the block of a preamble character in double succession, circuits for successively decoding each character and the same character in repetition, circuits for sorting the characters into correct and incorrect characters after verification of the parity code and the identity - bit by bit - of the character and its recovery, and a sort control circuit characterized by a counter for setting a preamble search period substantially equal to twice the duration of the preamble by a preamble detector which provides a first preamble detection signal when it receives a preamble has detected characters, and a second preamble detection signal, when it has detected its repetition, and by synchronizing and unlocking circuits for synchronizing the decoding circuits and for unlocking the sorting control circuit by the first, the second or both preamble detection signal (s). 2. Arrangement according to claim 1, characterized in that the sorting circuit for sorting the characters in correct and incorrect characters according to verification of the parity code and the identity bit by bit of the character 509824/0802 and its repetition comprises an output interface (24) for connection to a processing circuit (16) and circuits for detecting the arrival of the first information character at the interface and for generating it a signal corresponding to the end of the sorting of the first character and that the circuit for unlocking the character sorting control circuit is driven in an instant between the first preamble detection signal, if this has been detected or the second preamble detection signal if this has been detected has been, but not the first, and the mentioned sorting end signal of the first information character the character sorting control circuit only a moment after the moment of occurrence of the sorting end signal of the first information character to be able to unlock. 3. Arrangement according to claim 1, characterized in that that the information characters and their repetitions are the preamble and its repetition on the magnetic tape are recorded in a phase-coded manner. 4. Arrangement according to claim 1, characterized in that the character sorting circuit for sorting the characters into correct and incorrect characters, two parity code verification circuits which are each assigned to the character read first and the repeated character and a bit-by-bit comparator of the first read and repeated character as well as a selection circuit which selects the first read character if its parity code is correct, the repeated character, if its parity code is correct, that of the character read first however not, and the repeated character along with - 18 - 509824/080 an error signal if the parity code of the character read first and its repetition are both wrong and the two characters do not match in every bit. 509824/0802 JS L e r s e i t e