JPS6346890B2 - - Google Patents

Abstract

A data recording method in which serial data is recorded in blocks on a tape at a rate much higher than the data rate. Following recording (at 39) of a data block 40, tape motion is reversed (at 42) so that on recording of the next data block 40' the tape may be accelerated (45 to 38') to recording speed and the next data block recorded with a minimum gap between the blocks. The recorded data block is read and compared with the information which was recorded to verify operation of the recorded. The serial data is compared with a standard to verify validity. <IMAGE>

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording method and apparatus, particularly for incrementally recording data in closely spaced blocks for efficient use of recording media and for verifying the recorded data. METHODS AND APPARATUS.

Types of storage devices used for long-term data processing, such as tape drives for aircraft flight data storage, are subject to contradictory constraints in design and operation. The average recording speed must be low so that tape size and weight are not excessive. However, operation at low recording speeds is undesirable for several reasons. (1) Relaxation vibrations occur in the tape as it moves across the transducer head. This is sometimes referred to as the slip/stick phenomenon, where the tape sticks to the surface of the head, then slips across the head, and then sticks again. This causes tape motion to be intermittent at speeds higher than the average tape speed.

(2) Vibration induces flutter. This is a particularly troublesome phenomenon in the case of vehicle recording devices. This flutter is inversely proportional to tape speed.

(3) A separate read head is required if verification of recorded information is required. Additionally, the read or playback output is low level and susceptible to noise interference at low tape speeds.

(4) If high speed playback is required, a two speed tape drive is required. This not only makes the recording device complex and increases its size and weight, but also causes maintenance problems and increases costs.

Incremental operations, in which very short blocks of data are recorded intermittently, use the tape less efficiently because the length of tape used for gaps between records is large compared to the length of tape over which the data is recorded. Become. It also reduces the efficiency of copying information from tape.

According to the present invention, the above problems are overcome,
A recording method and apparatus are proposed for a reliable data tape recording device that allows verification of recorded data.

According to an essential feature of the invention, blocks of data are recorded as the recording medium passes through a transducer. The motion is then reversed to bring the recording medium and transducer into position for recording the next data block. Then, the movement is performed again and the next data block is recorded with the gap between data blocks as small as possible.

According to another feature of the invention, the actual speed between the recording medium and the transducer during recording is significantly higher than the average speed. Thus, recorded data can be reproduced in a fraction of the time the data was recorded by operating the device continuously at the recording speed.

According to another feature of the invention, each recorded data block is read and verified or checked before recording the next data block.

Other features and advantages of the invention will be readily apparent from the following detailed description, taken in conjunction with the accompanying drawings.

In this specification, digital data for aircraft using magnetic tape as a recording medium will be described.
Although the description will be made assuming that the present invention is applied to a recorder, it goes without saying that the present invention can be applied to other uses, and that other types of recording media can also be used.

With particular reference to FIG. 1, digital and analog signals from the aircraft are connected to inputs of flight data acquisition device 25. These signals represent various parameters of aircraft operation that it is desirable to record, such as altitude, air velocity, pitch angle, control element positions, engine parameters, etc.
In the flight data acquisition system, the analog signals are converted to digital form and the various digital signals are time multiplexed and output on an output line 26 which is connected to a serial-to-parallel converter 27. Digital data is accumulated in storage registers and provided to parallel-to-serial data converter 28 to form data blocks as described below.

Magnetic recording tape 30 is movable between reels 31 and 32 through a magnetic read/write transducer 33. When one data block is ready for recording, the tape drive 34 is activated to move the tape 30 through the transducer 33 so that the serial data is transferred to the parallel data via the write line 35.
It is supplied from the serial converter 28 to the converter 33. This data is recorded on tape at a speed significantly higher than that at which serial-to-parallel converter 27 is subjected. After recording the data block, the tape drive is stopped.

Next, the movement of the tape will be explained in detail with reference to FIGS. 2 and 3. These figures depict tape speed as a function of displacement. The tape starts from a stationary state at 37 and accelerates until the recording speed reaches 38. The tape advances to point 39 where data block 40 is written.
The tape drive then decelerates the tape to a stop at point 42. The direction of tape movement is then reversed and the tape is accelerated from point 42 to point 43. The tape moves in the opposite direction to point 44,
There, it is decelerated and stopped at point 45. The next data block is then written in a manner similar to that shown in FIG. The motion of the tape is point 45
Starting at , the tape is accelerated in the forward direction to point 38'. Data block 40 passes through converter 33 and at a predetermined position following data block 40, data block 40' is written. The tape drive is again decelerated to point 42', stopped there, then reversed direction and accelerated to point 43', reaching point 4.
The tape is moved to point 4', then decelerated and stopped at point 45'. The location of the next succeeding data block is indicated by a dashed line at 40'.

Tape speed can be selected to avoid problems with slipping/sticking and further minimize vibration-induced flutter regardless of data acquisition speed. Furthermore, reasonable accelerations and decelerations can be used, and the space between successive data blocks (interrecord gap or IRG) can be minimized to ensure efficient tape utilization.

Data block 40 passes transducer 33 while the tape moves in the opposite direction between points 43' and 44'. Stop point 45 is such that point 38' is before the leading edge of data block 40 in successive recording cycles, and in the forward direction data block 40 passes through transducer 33 before data block 41 is recorded. selected as follows.
During one pass of the data block 40 through the converter 33, the recorded information can be read out and verified by comparison with the recorded data. Referring again to FIG. 1, comparator 49 has an input connected to write line 35 and read line 5.
It has the other input connected to 0. An error signal is generated if the data written to the tape does not match the data read from the tape.

A playback control section 52 is connected to the tape drive section 34 for the purpose of continuously moving the tape in order to read recorded data. The movement of the tape in this case is preferably performed at the same speed as the data was recorded. Switch 53 is actuated by playback control 52 to couple the recording signal from read line 50 to the output device.
The recorded signal read from this output device can be copied or used for other purposes.

In one embodiment of the invention, the data blocks have a length L _D of 0.42 inches and an interrecord gap of 0.06 inches. In this case 87.5%
A recording density of . Please refer to FIGS. 3 and 4. Additionally, it should be noted that the size of the interrecord gap is dependent on tape speed.

In the illustrated embodiment of the invention, the tape speed during recording (and tape reversal) is 6 inches per second. However, the average tape speed is only 0.48
It's just inches per second. The continuous serial data from the flight data acquisition device has a bit rate of 768 bits per second (BPS). Data is accumulated for one second and blocks of 768 bits are recorded at a rate of 11.2K bits/second. Recorded data can be copied or transcribed in a fraction of the recording time by continuously running the tape. Typically, several data tracks are recorded sequentially on a single tape. All tracks can be copied simultaneously, thereby minimizing the amount of time the recording device is unavailable for use on an aircraft.

Preferably, the recording device is controlled by a programmed microprocessor. FIG. 5 shows data source and read/write converter 33, buffer registers 55, 56 and 57, storage registers 59 consisting of central processing unit (CPU) 58 and RAM (Random Access Memory) registers.
-64. It should be noted that the circled numbers in FIG. 5 represent events or sequences of events that occur during the reception, recording, and verification of one data block, as described below.

Registers 55, 56 form a programmable communication interface (PCI) that is a synchronous receive and transmit unit. The receiver provides data from the flight data acquisition device 25 to the CPU 58 and RAM registers, while the transmitter 56 provides data from these registers and the CPU to the converter 33. Register 57, which is part of the System Timing Controller (STC), stores data to verify or confirm records as described below.
Supplied to the CPU and registers 63 and 64.

The data (steps) on line 26 from the flight data acquisition system are in continuous two-phase form at a bit rate of 768 BPS and are shown in FIG. 6A. The two-phase demodulator 66 converts the data into NRZ (non-return-to-zero) format in steps using a clock signal or a strobe signal, as shown in FIG. 6B ₁ and B ₂ . Data and strobe signals are sent to reception buffer 5.
5, and the buffer 55 transfers the serial data to 8
The 8-bit bytes are transmitted in parallel to the CPU 58 in steps. Note that the buffer 55 is shown as a single element to simplify the illustration. However, in reality, it is two steps wide, and 1 byte of data is
The serial input data is not dropped or lost while being transmitted to the CPU 58. Similarly, it is preferable that the buffers 56 and 57 have a double width.

RAM registers 61 and 62 are each
Represented by BUFERA and BUFERB. Each register has a capacity of 96 bytes. The received data is 96 bytes or 768 bytes in steps.
One of the registers until the bit is stored, e.g.
Collected in BUFERA. This data is data received within 1 second. Thereafter, as will become clear, the data in the filled buffer register is transmitted for recording, while the input data is stored in other BUFERBs.

In the CPU, preambles and postambles are appended to data blocks to facilitate identification in subsequent analysis of the data. These preamble and postamble each consist of seven "0"s and one "1".

The RAM register 60 represented by CHKSUM is
It has a capacity of 2 bytes and receives information characterizing the received data at the step. Specifically, the CHKSUM register has a bit capacity equal to 787 plus the sum of "1" bits occurring in a 1 second block of received data. Here 787 is "0" data with preamble and postamble.
This is the number of bits with the polarity of 768 bits reversed.
CHKSUM is compared to a reference value to check the validity of the received data. In step 2
The number representing CEHKSUM divided by
It is stored in the CHEKIN register 59.

Once the BUFERA register is full, a recording operation begins. At the same time, the input data
Sent to BUFERB. The received data in BUFERA is sent in steps to the transmit buffer 56 along with the preamble and postamble. The 8 bits of each byte are simultaneously fed into a register where they
Timing output from registers at a bit rate of 11.2K bits/second. Serial data from buffer 56 in NRZ format is transmitted to two-phase modulator 6.
7. This modulator 67 produces an output in two-phase form at a rate of 11.2K bits/second.
(See steps). When BUFERA is empty, all data has been transmitted and the formation of the data block to be recorded is complete.

The signal on line 68 shown in FIG. 6C is a short block of data in a two-phase format where the data bits correspond to one second of received data plus a preamble and postamble. This short block data signal is provided to converter 33 via write amplifier 69 and to tape 3.
recorded on 0. During write operation, switch 72
is in the WR position, and the signal on line 68 is on line 73.
and is supplied to the CPU via the 8-stage register 57. Steps, and references. Positive transitions of data are counted and the number is stored in CHEKWR register 63. Step. CEHEKWR
is compared with CHEKIN to verify that the recorded data is accurate.

During the reading of previously written data blocks as described above in connection with FIG.
Connected to RD position. Step. converter 33
The recorded data read out by (FIG. 6D) is supplied to register 57 via read amplifier 75, switch 72 and line 73. Step.
The output side of the register is connected to the CPU 58 (step), and the number representing a positive signal transition is
CHEKRD register 64 is provided. Step. This number is compared with CHEKWR from register 63 and CHEKIN from register 59 to verify the recording and playback of the data signal.

Next, the operation of the data recording apparatus will be further explained with reference to flowcharts shown in FIGS. 7 to 17.

The overall operation is summarized in FIG. Operation begins with a system reset upon power up (step 80). This system is a step
Defaults to 81. At step 82 the operating mode is determined. If the system is in standby, the program returns to the initial settings (steps
81). If in flight record mode, flight record control is bypassed at step 83. Serial data is received from the flight data acquisition device and is processed in step 84.
Supplied to BUFERA or BUFERB. Data continues to be sent to the buffer (step 85) unless 768 data bits are received. Once 768 data bits have been received, the program moves to step 86. The received data is sent to other RAM buffers. The tape is moved forward, the previous data block is verified, and the data in the now full buffer is recorded to the tape. In step 87, if the end of tape is not detected, the received data continues to be stored in the RAM buffer and tape movement in the reverse direction is performed as described in connection with FIGS. 1, 2, and 3. (Step 88). In step 89, a check is made as to whether there is a standby mode command. If this instruction is not present, the program will proceed to step 84.
and repeat the above steps. If there is a standby instruction, the program returns to step 81.

When the end of tape is detected in step 87, the program proceeds to step 90 where a track selection is made and the tape is moved to the next track on the multi-track tape for a sufficient length to erase old data. to enable recording of the next data block.

At step 82, an external device mode selection is made for various operations that may be used to examine the recorded data, transcribe it to another tape, or transfer it to an external computer or the like. Since such functions are not related to the present invention, they will not be described in detail here. At step 92, external device control for the selected mode or submode is initiated. These modes include the following modes:

(a) Rewind mode to the beginning of the tape (b) Forward mode to the end of the tape (c) Continuous run in normal direction (d) Continuous run in non-normal direction Selected sub-mode in step 93 The operations include controlling tape motion, controlling read/write operations, and switching tape tracks as necessary. In step 94, it is determined whether the selected mode or sub-mode is complete. If not, the operation continues with step 93 as determined. If the selected mode has been completed, the program returns to step 81.

FIG. 8 shows a simplified flowchart of the flight recording mode FLTREC. This figure provides an overview of the functions described in more detail in conjunction with FIGS. 9-15. Upon entry to the FLTREC operation, a RAM buffer to store the received data is selected in RDSET step 96 and other circuits are initialized. When a data block is created, this data block is recorded in FSTROK97. Following this recording, a determination is made as to whether the end of the tape has been reached, and if so (which is usually the case) tape winding or checking (CSTROK) is initiated at step 99. The program then continues up to RDWAIT step 100 until the data has been completely accumulated in the buffer. When the end of the tape is detected in step 98, the CSTROK step 99 is omitted in step 101 and track switching is performed by another program (not shown).

Details of the flight recording function FLTREC are shown in the flowchart in Figure 9. The PCI receiving section 55 is cleared and initialized in step 105. Erase control is enabled in step 106, thereby erasing old data from the tape before recording new data blocks. In step 107, it is determined whether a write operation is currently in progress. If no write is in progress,
Assign BUFERA and BUFERB in step 108
The program is switched to step 109.
Proceed to the RDSET submodule. This will be discussed in detail later with reference to FIG. If writing is in progress at step 107,
Step 108 is omitted and the program continues to step
Proceed to 109.

In step 110, progressive FSTRK is initiated to verify or check previously written data blocks. This will be explained in detail in conjunction with FIG. step
Step 111 corresponds to step 98 in FIG. 8, and a check is made as to the presence or absence of a tape end signal. If a track change is not required at step 112, the program proceeds to step 113 where the tape direction is reversed. This will be explained in detail later with reference to FIG. If tape switching is required, step
113 will be diverted. In step 114 a check is made as to whether the standby mode of operation is present.
If not in standby mode, the program proceeds to step 115 (RDWAIT). This step will be described in detail in conjunction with FIG. The program then returns to step 108 when the next data block is received by PCI receiver 55.

In step 118, where FIG. 10 illustrates the functions performed during the RDSET submodule in setting assignments for BUFERA/BUFERB, a determination is made whether BUFERA is the designated receive key buffer. Step 119,
120, the address of the associated buffer is
A RAM register (not shown) is stored to indicate which buffer the received data should be sent to for storage. In step 121,
CHECKSUM register 60 is cleared and set to an initial value of 787, ready to receive characteristic information regarding the input data. In step 122, one byte is cleared from the full RAM buffer to TCI transmitter 56, and loop 123 is executed until all bytes are cleared.
The RDSET submodule is thus completed and control is returned to the FLTREC program.

FSTROK submodule 110 is shown in FIG. This program initializes the system for write operations, verifies previously recorded data blocks, and buffers A/B6
Steps are taken to record data from the buffer that is full. In step 126, a determination is made as to which buffers are full and when, and a selection of buffers is made for recording data to tape. The associated buffer pointer is set and stored at step 127. Then, in step 128, the track number in use on the tape is determined and thereby the direction of tape movement for recording is determined. At step 129, the associated motor control flags are stored. At step 130, the tape drive motor is started and accelerated to the speed used for reading and writing.

The tape drive motor is a polyphase reversible step motor. Counting the steps or advances of the step motor allows accurate measurements of tape speed and tape position during acceleration and deceleration.

In step 131, playback of previously recorded data is initiated and motor step counting continues until the interrecord gap indicates that transducer 33 has been reached. step
At 133, playback is disabled and a signal characterizing the playback data is stored in CHKRD register 64. In step 134,
Data characteristic information in CHKIN and CHEKWR registers 59, 63, respectively, are compared. If the information matches, a data processing error register (not shown) is cleared at step 135.
If they do not match, a count of one is added to the error register at step 136. At step 137
The data characteristic information in the CHEKRD register 64 is
It is compared with the information in the CHEKWR register 63.
If the information matches, a zero is shifted into the CHEKER register (not shown), and if they do not match, a "1" is shifted into the CHEKER register to generate a data check error output signal. In step 140, a determination is made whether the CHEKER register indicates eight consecutive errors. If not, the M error register is cleared in step 141. Conversely, if there are eight consecutive errors, this is recorded in the M error register at step 142.

Motor step counter 145 determines when the end of the interrecord gap is reached. At step 146, PCI data transmitter 56 is activated and write current is provided to converter 33. Motor step counter 147 identifies the end of the data block. Transmission of data from PCI transmitter 56 ends at step 148. Motor drive is stopped at step 149 and the write current is cut off at step 150. The data in CHEKWR register 63 is saved.

The program shown in FIG. 12 is for tape reversal movement and is expressed in CSTROK notation. In steps 155 and 156, the track number is determined and the correct motor direction control flag is set.
The associated flags are stored in step 157. At step 158 the motor is started and accelerated. The steps or advances of the motor are counted in step 159, and when the motor reaches the relevant count,
In step 160, the speed is decelerated and stopped. As a result, the tape is positioned at point 45 in FIG.
A state is reached in which the FSTROK operation (FIGS. 11A and 11B) can be performed.

Figure 13 is element 115 of Figure 9.
It illustrates the program for the RDWAIT submodule. In step 163, a data loss counter is initialized. If the counter times out before receiving the data-filled buffer signal, an error condition is established. Following the initialization of the counter, the program monitors the receive buffer 55 and the counter in steps 164 and 165. If the receive buffer is full before the data loss counter is filled, the recorder status error is set to zero in step 166, CHEKSUM is checked in steps 167 and 168, and
and 1555 limits is determined.
If CHEKSUM is correct, the data processing error flag is cleared in step 169, and the CHEKSUM data is cleared in step 170.
Transferred to CHEKIN register 59.
If CHEKSUM is outside its limits, an error flag is set in step 171.
If the data loss counter overflows, an error flag is set at step 172.

FIG. 14 shows the submodule RXRDY, which is executed as an interrupt procedure to transfer received aircraft data from PCI register 55 to a designated one of BUFERA/BUFERB and perform other related functions. Show the program. In step 175, the data is transferred from the PCI register to
selected in steps 119 and 120 (Figure 10)
Transferred to RAM buffer. A procedure is performed to generate a CHEKSUM for each byte of data, each 8 bits, transferred to the buffer. At step 176, a register (not shown)
is set to "8" corresponding to 8 bits of data. In steps 177 and 178, CHEKSUM is incremented for each bit in the received data.
In step 179, the register is decremented for each data bit test. register steps
When it reaches zero at 180, CHEKSUM is stored at step 181. At step 182, the status of the receive buffer is checked. If it is not full,
A buffer pointer is incremented at step 183.
When the buffer is full, the associated status flag is set at step 184.

A submodule that is another interrupt process
TXRDY is shown in FIG. This program is used to transfer data to be recorded on tape from the buffer to the registers of the PCI transmitter 56. At step 188 a byte counter (not shown) is incremented. This counter is
Records the number of bytes transferred from the buffer to the data transmitter. Count is 97 in step 189
If so, the next data byte is sent to the PCI transmitter 56 data register at step 190. 97 bytes (with preamble
96 data bytes) are transmitted, this count is identified in step 191 and the postamble and preamble are sent to the PCI register in step 192. If the count exceeds 97, the TXRDY interrupt is disabled at step 193 and the write operation is terminated.

The specific programs briefly described above are merely provided to explain the general operation of the data recording device using the present invention. It should be noted that many of the detailed procedures and tests that are desirable for commercially available products are not related to the present invention and have been omitted here as they would be unnecessary and complicated. .

Further, other aspects of the data recording device related to data acquisition and playback and copying operations are described in the patent application filed concurrently with the present application.

[Brief explanation of drawings]

FIG. 1 is a simplified block diagram of a recording device illustrating the invention, FIGS. 2 and 3 are velocity-displacement graphs to illustrate the invention, and FIG. 4 is a diagram illustrating a series of data blocks. FIG. 5 is a block diagram showing in more detail the apparatus for implementing the present invention shown in FIG. 1, FIG. 6 is a diagram for explaining the operation, and FIGS. 10
Fig. 11A, Fig. 11B, Fig. 12, Fig. 13
14 and 15 are flowcharts illustrating preferred embodiments of carrying out the invention. 25... Flight data acquisition device; 27... Series-parallel converter; 26... Output line; 28... Parallel-serial data converter; 30... Magnetic recording tape;
33...Magnetic read/write converter; 31, 32
... Reel; 34 ... Tape drive section; 35 ... Write line; 40 ... Data block; 55,5
6, 57...Buffer register; 58...Central processing unit (CPU); 59-64...Storage register; 66...Two-phase demodulator; 67...Two-phase modulator;
69...Amplifier.

Claims (1)

[Claims] 1. A method for recording serial data in a continuous data block state on a recording medium that moves relative to a data converter and for verifying the accuracy of the recording. To: accept serial data; divide the received serial data into a plurality of blocks; store characteristic values of one data block; record the data block; record the data block; reading the recorded data block; storing the characteristic value of the read data block; and storing the two stored characteristic values. verifying said recorded data block by comparing said data blocks; 2. A device for recording serial data in a block state and verifying the accuracy of the recorded data, comprising: means for dividing the serial data into a plurality of data blocks; means for detecting the characteristic value of the data block; a first register connected to the detection means for storing the characteristic value of the detected data block; a recording medium; the serial data with a speed several times that of
Means for recording the data block on the recording medium; Means for detecting the characteristic value of the data block while a recording operation is being performed; Means for detecting the characteristic value of the recorded data block. a second register for storing; means for reading the recorded data block; means for detecting characteristic values of the read data block; and a second register for each of the first and second registers. means for verifying said recorded data block by comparing stored characteristic values.