GB1398940A - Method of dividing semiconductor wafers - Google Patents

Method of dividing semiconductor wafers

Info

Publication number
GB1398940A
GB1398940A GB3238173A GB3238173A GB1398940A GB 1398940 A GB1398940 A GB 1398940A GB 3238173 A GB3238173 A GB 3238173A GB 3238173 A GB3238173 A GB 3238173A GB 1398940 A GB1398940 A GB 1398940A
Authority
GB
United Kingdom
Prior art keywords
plasma
gas
wafer
freon
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3238173A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of GB1398940A publication Critical patent/GB1398940A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Perforating, Stamping-Out Or Severing By Means Other Than Cutting (AREA)
  • Dicing (AREA)

Abstract

1398940 Removing material by gas plasmas MITSUBISHI DENKI KK 6 July 1973 [8 July 1972] 32381/73 Heading B3V [Also in Divisions B5 H1 and B6] A semi-conductor wafer is divided by forming one or more grooves using the etching action of a Freon (R.T.M.) gas plasma and by subsequently separating the parts defined by the groove(s). A silicon wafer containing a plurality of integrated circuits, transistors, thyristors or diodes may be photoresist masked and then plasma etched along sets of intersecting grooves. The Freon gas may be mixed with argon, helium, neon or krypton. The etching rate may be controlled by the overall pressure, by the ratio of Freon to inert gas, or by the power supplied at high frequency to the plasma. The photoresist may be removed by normal etching or by the use of an oxygen plasma. The wafer is divided by hand, by the application of a differential pressure to the faces of the wafer (making it a wall of a vacuum chamber), or by ultrasonic action.
GB3238173A 1972-07-08 1973-07-06 Method of dividing semiconductor wafers Expired GB1398940A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6839872A JPS523775B2 (en) 1972-07-08 1972-07-08

Publications (1)

Publication Number Publication Date
GB1398940A true GB1398940A (en) 1975-06-25

Family

ID=13372538

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3238173A Expired GB1398940A (en) 1972-07-08 1973-07-06 Method of dividing semiconductor wafers

Country Status (4)

Country Link
JP (1) JPS523775B2 (en)
DE (1) DE2334658C3 (en)
FR (1) FR2192378B1 (en)
GB (1) GB1398940A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003036712A1 (en) * 2001-10-19 2003-05-01 Applied Materials, Inc. Method and apparatus for dicing a semiconductor wafer
CN103341692A (en) * 2013-06-26 2013-10-09 京东方科技集团股份有限公司 Method for cutting irregular figure substrate and display device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0644592B2 (en) * 1984-10-25 1994-06-08 日本電気株式会社 Method for manufacturing semiconductor device
JP7102065B2 (en) * 2018-06-20 2022-07-19 株式会社ディスコ Chip manufacturing method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3615956A (en) * 1969-03-27 1971-10-26 Signetics Corp Gas plasma vapor etching process

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003036712A1 (en) * 2001-10-19 2003-05-01 Applied Materials, Inc. Method and apparatus for dicing a semiconductor wafer
CN103341692A (en) * 2013-06-26 2013-10-09 京东方科技集团股份有限公司 Method for cutting irregular figure substrate and display device
US9416041B2 (en) 2013-06-26 2016-08-16 Beijing Boe Display Technology Co., Ltd. Method for cutting substrate of irregular pattern and display device
US10414683B2 (en) 2013-06-26 2019-09-17 Boe Technology Group Co., Ltd. Method for cutting substrate of irregular pattern and display device

Also Published As

Publication number Publication date
FR2192378A1 (en) 1974-02-08
DE2334658C3 (en) 1978-11-23
FR2192378B1 (en) 1977-09-02
JPS4928270A (en) 1974-03-13
DE2334658B2 (en) 1978-03-30
DE2334658A1 (en) 1974-01-24
JPS523775B2 (en) 1977-01-29

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Legal Events

Date Code Title Description
PS Patent sealed
PE20 Patent expired after termination of 20 years

Effective date: 19930705