GB1391640A - Semi conductor memory device - Google Patents

Semi conductor memory device

Info

Publication number
GB1391640A
GB1391640A GB5776672A GB5776672A GB1391640A GB 1391640 A GB1391640 A GB 1391640A GB 5776672 A GB5776672 A GB 5776672A GB 5776672 A GB5776672 A GB 5776672A GB 1391640 A GB1391640 A GB 1391640A
Authority
GB
United Kingdom
Prior art keywords
substrate
region
electrode
film
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5776672A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Publication of GB1391640A publication Critical patent/GB1391640A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

1391640 Semiconductor memory devices MATSUSHITA ELECTRONICS CORP 14 Dec 1972 (17 Dec 1971 (2)] 57766/72 Heading H1K A semiconductor memory device (Fig. 4) comprises a P-type Si substrate 1 with aN-type indiffused region 2 forming a PN junction therewith. A thin SiO2 film on the remainder of the surface is covered by a film of Si3N4, and metal electrode 6 is in ohmic contact with the region 2 while an annular metal electrode 5 overlies the insulant layers. A highly doped N<+> region 10 with a stepped structure of high concentration is provided in the surface of the substrate. A reverse voltage from supply V (Fig. 5) initially biases the PN junction in reverse sense for logic 0 and then a voltage negative referred to the substrate from supply V2 is applied to electrode 5 for logic 1. Electrons in the trap level of film 4 are injected into the substrate surface by tunnel effect through film 3 to form an inversion layer 7 in the substrate surface. Removal of V2 leaves the inversion layer in situ attracted by the corresponding positive charge layer 8 in film 4 and this condition persists for the lifetime of the deep level trap in film 4. For readout, V2 is cut off and V1 is applied to electrode 6 and the level of the reverse saturation current is low for logic 0 and is increased for logic 1 due to inversion layer 7 (Fig. 6, not shown) and formation of the inversion layer 7 on write-in causes conduction between region 10 and the central indiffused region 2; while on readout application of reverse bias to the junction electrode 6 the resultant current is increased by break-down between the peripheral region 10 and the substrate 1. Erasure is produced by applying voltage V3 between electrodes 5, 11 in reverse sense to the write-in voltage. In fabrication the impurity doped substrate is masked with SiO2 on its (100) plane surface which is windowed for indiffusion of P to form a circular N-type region. After removal of the mask, an insulant film of SiO2 is vapour deposited thin enough for punch-through and a similar Si3N4 film is deposited therein by thermo-decomposition of vapourized ammonia + silane, after which the electrodes are formed by deposition and photoetching of Al. An electrode of Au-Ga is deposited on the back of the substrate and a high concentration N<+> stepped region 10 is provided in the periphery of the device by deposition through a windowed SiO2 mask, N-type Si may replace P-type Si for the substrate, when the second insulant film must have a deep acceptor level and may be of TiO2, HfO2 Ta2O3 or Al2O3 and the voltage polarities must be reversed. In a further modification (Fig. 7) the N<+> region is replaced by a P<+> region 20 with a metal electrode 21 acting as read-out electrode so that write in and erase are performed by voltage between electrode 5 and back electrode 7, and readout by voltage between electrode 21 and electrode 2 on region 2; and the inversion layer on substrate 1 produced by write-in connects the regions 20, 2 so that breakdown occurs at a low read out voltage. A N-type substrate may replace the P-type substrate with a thin SiO2 insulant layer capable of punch through, with a trap level formed therein covered with an insulant film 4 of TiO2, HfO2, Ta2O3 or Al2O3 having an acceptor level.
GB5776672A 1971-12-17 1972-12-14 Semi conductor memory device Expired GB1391640A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10308271A JPS4866943A (en) 1971-12-17 1971-12-17
JP10308371A JPS5144869B2 (en) 1971-12-17 1971-12-17

Publications (1)

Publication Number Publication Date
GB1391640A true GB1391640A (en) 1975-04-23

Family

ID=26443741

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5776672A Expired GB1391640A (en) 1971-12-17 1972-12-14 Semi conductor memory device

Country Status (6)

Country Link
JP (2) JPS5144869B2 (en)
CA (1) CA1000404A (en)
DE (1) DE2261522C3 (en)
FR (1) FR2163682B1 (en)
GB (1) GB1391640A (en)
NL (1) NL163064C (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2351843A (en) * 1999-06-25 2001-01-10 Lucent Technologies Inc Charge injection transistor using high-k dielectric barrier layer

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53150469U (en) * 1977-05-02 1978-11-27
JPS5484575U (en) * 1977-11-29 1979-06-15
JPS555478U (en) * 1978-06-26 1980-01-14
JPS617816U (en) * 1984-06-19 1986-01-17 松下電器産業株式会社 push button device
JPH06326323A (en) * 1993-05-14 1994-11-25 Nec Corp Nonvolatile tunnel transistor and memory circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2791761A (en) * 1955-02-18 1957-05-07 Bell Telephone Labor Inc Electrical switching and storage
CA813537A (en) * 1967-10-17 1969-05-20 Joseph H. Scott, Jr. Semiconductor memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303940B1 (en) 1999-01-26 2001-10-16 Agere Systems Guardian Corp. Charge injection transistor using high-k dielectric barrier layer
GB2351843A (en) * 1999-06-25 2001-01-10 Lucent Technologies Inc Charge injection transistor using high-k dielectric barrier layer
GB2351843B (en) * 1999-06-25 2001-09-26 Lucent Technologies Inc Charge injection transistor using high-K dielectric barrier layer

Also Published As

Publication number Publication date
NL7217144A (en) 1973-06-19
FR2163682A1 (en) 1973-07-27
FR2163682B1 (en) 1976-10-29
CA1000404A (en) 1976-11-23
DE2261522A1 (en) 1973-07-12
JPS4866943A (en) 1973-09-13
JPS5144869B2 (en) 1976-12-01
NL163064B (en) 1980-02-15
NL163064C (en) 1980-07-15
JPS4866944A (en) 1973-09-13
DE2261522B2 (en) 1977-07-07
DE2261522C3 (en) 1982-03-04

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Legal Events

Date Code Title Description
PS Patent sealed
746 Register noted 'licences of right' (sect. 46/1977)
PE20 Patent expired after termination of 20 years

Effective date: 19921213