GB1230421A - - Google Patents

Info

Publication number
GB1230421A
GB1230421A GB1230421DA GB1230421A GB 1230421 A GB1230421 A GB 1230421A GB 1230421D A GB1230421D A GB 1230421DA GB 1230421 A GB1230421 A GB 1230421A
Authority
GB
United Kingdom
Prior art keywords
polyimide
semi
film
photoresist
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1230421A publication Critical patent/GB1230421A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/094—Multilayer resist systems, e.g. planarising layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
GB1230421D 1967-09-15 1968-08-29 Expired GB1230421A (US07902200-20110308-C00004.png)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US66808067A 1967-09-15 1967-09-15
US2680670A 1970-04-08 1970-04-08

Publications (1)

Publication Number Publication Date
GB1230421A true GB1230421A (US07902200-20110308-C00004.png) 1971-05-05

Family

ID=26701675

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1230421D Expired GB1230421A (US07902200-20110308-C00004.png) 1967-09-15 1968-08-29

Country Status (4)

Country Link
US (1) US3700497A (US07902200-20110308-C00004.png)
FR (1) FR1580665A (US07902200-20110308-C00004.png)
GB (1) GB1230421A (US07902200-20110308-C00004.png)
NL (1) NL6813133A (US07902200-20110308-C00004.png)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0188735A1 (en) * 1985-01-22 1986-07-30 International Business Machines Corporation Tailoring of via-hole sidewall slope in an insulating layer
EP0261400A2 (en) * 1986-08-27 1988-03-30 Hitachi, Ltd. Lift-off process for forming wiring on a substrate

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3787207A (en) * 1971-12-16 1974-01-22 Matsushita Electric Ind Co Ltd Electrophotographic photosensitive plate having a polyimide intermediate layer
US3911475A (en) * 1972-04-19 1975-10-07 Westinghouse Electric Corp Encapsulated solid state electronic devices having a sealed lead-encapsulant interface
US4001870A (en) * 1972-08-18 1977-01-04 Hitachi, Ltd. Isolating protective film for semiconductor devices and method for making the same
US4017886A (en) * 1972-10-18 1977-04-12 Hitachi, Ltd. Discrete semiconductor device having polymer resin as insulator and method for making the same
JPS5131185B2 (US07902200-20110308-C00004.png) * 1972-10-18 1976-09-04
US3952324A (en) * 1973-01-02 1976-04-20 Hughes Aircraft Company Solar panel mounted blocking diode
DE2326314C2 (de) * 1973-05-23 1983-10-27 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung von Reliefstrukturen
JPS5527463B2 (US07902200-20110308-C00004.png) * 1973-02-28 1980-07-21
JPS5754043B2 (US07902200-20110308-C00004.png) * 1973-05-21 1982-11-16
JPS5012973A (US07902200-20110308-C00004.png) * 1973-06-01 1975-02-10
US3869704A (en) * 1973-09-17 1975-03-04 Motorola Inc Semiconductor device with dispersed glass getter layer
US3873361A (en) * 1973-11-29 1975-03-25 Ibm Method of depositing thin film utilizing a lift-off mask
JPS5421073B2 (US07902200-20110308-C00004.png) * 1974-04-15 1979-07-27
DE2428373C2 (de) * 1974-06-12 1982-05-27 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Herstellen von weichlötbaren Anschlußkontakten auf einer Halbleiteranordnung
US4218283A (en) * 1974-08-23 1980-08-19 Hitachi, Ltd. Method for fabricating semiconductor device and etchant for polymer resin
US4113550A (en) * 1974-08-23 1978-09-12 Hitachi, Ltd. Method for fabricating semiconductor device and etchant for polymer resin
JPS5131186A (US07902200-20110308-C00004.png) * 1974-09-11 1976-03-17 Hitachi Ltd
US3959047A (en) * 1974-09-30 1976-05-25 International Business Machines Corporation Method for constructing a rom for redundancy and other applications
DE2547792C3 (de) * 1974-10-25 1978-08-31 Hitachi, Ltd., Tokio Verfahren zur Herstellung eines Halbleiterbauelementes
DE2459665C2 (de) * 1974-12-17 1982-12-30 Siemens AG, 1000 Berlin und 8000 München Anordnung zum Herstellen eines Körperschnittbildes mit fächerförmigen Bündeln von Röntgenstrahlen
US3985597A (en) * 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface
US4086375A (en) * 1975-11-07 1978-04-25 Rockwell International Corporation Batch process providing beam leads for microelectronic devices having metallized contact pads
GB1563421A (en) * 1975-12-18 1980-03-26 Gen Electric Polyimide-siloxane copolymer protective coating for semiconductor devices
GB1585477A (en) * 1976-01-26 1981-03-04 Gen Electric Semiconductors
DE2638799C3 (de) * 1976-08-27 1981-12-03 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zur Verbesserung der Haftung von metallischen Leiterzügen auf Polyimidschichten in integrierten Schaltungen
US4140572A (en) * 1976-09-07 1979-02-20 General Electric Company Process for selective etching of polymeric materials embodying silicones therein
US4092442A (en) * 1976-12-30 1978-05-30 International Business Machines Corporation Method of depositing thin films utilizing a polyimide mask
US4244799A (en) * 1978-09-11 1981-01-13 Bell Telephone Laboratories, Incorporated Fabrication of integrated circuits utilizing thick high-resolution patterns
JPS5850417B2 (ja) * 1979-07-31 1983-11-10 富士通株式会社 半導体装置の製造方法
US4307179A (en) * 1980-07-03 1981-12-22 International Business Machines Corporation Planar metal interconnection system and process
DE3027941A1 (de) * 1980-07-23 1982-02-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von reliefstrukturen aus doppellackschichten fuer integrierte halbleiterschaltungen, wobei zur strukturierung hochenergetische strahlung verwendet wird
US4334949A (en) * 1980-11-25 1982-06-15 International Business Machines Corporation Reducing carbonate concentration in aqueous solution
US4423547A (en) 1981-06-01 1984-01-03 International Business Machines Corporation Method for forming dense multilevel interconnection metallurgy for semiconductor devices
DE3132452A1 (de) * 1981-08-17 1983-02-24 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen einer nach dem galvanischen aufbau von metallischen strukturen planaren strukturebene
US4411735A (en) * 1982-05-06 1983-10-25 National Semiconductor Corporation Polymeric insulation layer etching process and composition
JPS60501113A (ja) * 1983-04-22 1985-07-18 エム・アンド・テイ・ケミカルス・インコ−ポレイテツド 改良されたポリアミド酸およびポリイミド
US4495220A (en) * 1983-10-07 1985-01-22 Trw Inc. Polyimide inter-metal dielectric process
US4656050A (en) * 1983-11-30 1987-04-07 International Business Machines Corporation Method of producing electronic components utilizing cured vinyl and/or acetylene terminated copolymers
EP0162017B1 (de) * 1984-05-17 1991-08-21 Ciba-Geigy Ag Homo- und Copolymere, Verfahren zu deren Vernetzung und derenVerwendung
US4639277A (en) * 1984-07-02 1987-01-27 Eastman Kodak Company Semiconductor material on a substrate, said substrate comprising, in order, a layer of organic polymer, a layer of metal or metal alloy and a layer of dielectric material
US4599136A (en) * 1984-10-03 1986-07-08 International Business Machines Corporation Method for preparation of semiconductor structures and devices which utilize polymeric dielectric materials
US4568601A (en) * 1984-10-19 1986-02-04 International Business Machines Corporation Use of radiation sensitive polymerizable oligomers to produce polyimide negative resists and planarized dielectric components for semiconductor structures
US4693780A (en) * 1985-02-22 1987-09-15 Siemens Aktiengesellschaft Electrical isolation and leveling of patterned surfaces
US5284801A (en) * 1992-07-22 1994-02-08 Vlsi Technology, Inc. Methods of moisture protection in semiconductor devices utilizing polyimides for inter-metal dielectric
JP2698827B2 (ja) * 1993-11-05 1998-01-19 カシオ計算機株式会社 バンプ電極を備えた半導体装置の製造方法
US5723385A (en) * 1996-12-16 1998-03-03 Taiwan Semiconductor Manufacturing Company, Ltd Wafer edge seal ring structure
US7018776B2 (en) * 2002-12-12 2006-03-28 Arch Specialty Chemicals, Inc. Stable non-photosensitive polyimide precursor compositions for use in bilayer imaging systems
KR100510543B1 (ko) * 2003-08-21 2005-08-26 삼성전자주식회사 표면 결함이 제거된 범프 형성 방법
US7098544B2 (en) * 2004-01-06 2006-08-29 International Business Machines Corporation Edge seal for integrated circuit chips

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0188735A1 (en) * 1985-01-22 1986-07-30 International Business Machines Corporation Tailoring of via-hole sidewall slope in an insulating layer
US4624740A (en) * 1985-01-22 1986-11-25 International Business Machines Corporation Tailoring of via-hole sidewall slope
EP0261400A2 (en) * 1986-08-27 1988-03-30 Hitachi, Ltd. Lift-off process for forming wiring on a substrate
EP0261400A3 (en) * 1986-08-27 1989-05-24 Hitachi, Ltd. Lift-off process for forming wiring on a substrate
US4886573A (en) * 1986-08-27 1989-12-12 Hitachi, Ltd. Process for forming wiring on substrate

Also Published As

Publication number Publication date
US3700497A (en) 1972-10-24
DE1764977B1 (de) 1972-06-08
NL6813133A (US07902200-20110308-C00004.png) 1969-03-18
FR1580665A (US07902200-20110308-C00004.png) 1969-09-05

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees