GB1563421A - Polyimide-siloxane copolymer protective coating for semiconductor devices - Google Patents

Polyimide-siloxane copolymer protective coating for semiconductor devices Download PDF

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GB1563421A
GB1563421A GB52024/76A GB5202476A GB1563421A GB 1563421 A GB1563421 A GB 1563421A GB 52024/76 A GB52024/76 A GB 52024/76A GB 5202476 A GB5202476 A GB 5202476A GB 1563421 A GB1563421 A GB 1563421A
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semiconductor
protective layer
semiconductor element
polyimide
junction
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General Electric Co
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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    • H01L2924/181—Encapsulation

Description

(54) POLYIMIDE-SILOXANE COPOLYMER PROTECTIVE COATING FOR SEMICONDUCTOR DEVICES (71) We, GENERAL ELECTRIC COMPANY, a corporation organized and existing under the laws of the State of New York, United States of America, of 1 River boat, Schenectady 12305, State of New York, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to polymidesiloxane copolymers as protective coatings for semiconductor devices.
The coatings of selected surface areas of semiconductor devices with electrically insulating oxide materials has been a common practice. Such coatings are thin layers which have virtually no resistance to mechanical abrasion and require relatively expensive processing equipment. In almost all instances a second and a thicker protective layer is required to protect the initial layer. Known overcoatings of silicon greases, varnishes, rubbers and resins have had less than optimum physical characteristics. The most common failings have been inadequate adhesion, moisture permeability, permeability to mobile ions, and reactivity on the part of the coating material.
Robert R. Shaw. in U.S. Patent 3,615,913.
granted on October 28, 1971, teaches a cured, protective coating material selected from the group consisting of polyimides, and polyamide-polyimides disposed on exposed P-N junctions for passivation.
Although these materials exhibit good adhesion resistance properties, they tend to be too hard and to lack the necessary adhesive qualities to withstand the stresses of thermal shock.
There is currently widespread use of oxide/glass layers for passivation and encapsulation of semiconductor devices where device stability and long life are important considerations. However, if the glassy layer must be applied after aluminum metallization, (a widespread requirement), the choice of suitable glass systems is severely circumscribed by a maximum permissible application temperature of -577"C. This restriction is set by the aluminum-silicon eutectic and must be carefully observed in all processing operations following aluminization of the silicon.
Several glass coating methods are currently in use. These include chemical vapor deposition (CVD), glass frits, and spin-on glass forming alcoholates. The last method is only capablessof forming very thin layers, of the order of 2000he, of glasses which tend to be more reactive than desirable and, therefore, are of restricted utility in packaging. Glass frits are widely used in packaging but are not usually employed for surface passivation because of difficulties in formulating glasses with an adequate expansion match to silicon, and which are at the same time suitable passivants suitably homogeneous and chemically stable. CVD methods permit adequate thickness, a wide choice of composition, expansion matching, etc., but difficulties in controlling sodium contamination in CVD reactors have made it difficult to obtain acceptable passivation layers by direct deposition onto base silicon.
This method is, therefore, usually restricted to use as an overcoating of SiO2 and metallization layers. None of these methods in their current state of development is considered capable of providing a reliable passivation/encapsulation method for large thyristors and other power semiconductor devices.
Manufacturers of semiconductor elements prefer simple one-component materials which are easily applied and cured in situ for use in manufacturing a general line of semiconductor elements or devices.
Exotic materials, application techniques and cure cycles, as well as multiple coatings of the same or different materials, are employed only in those instances where function requires it and/or cost is no object.
Hoback and Holub in U.S. Patent 3,740,305, teach the use of a reaction product of an organic diamine, an organic tetracarboxylic dianhydride, and a polysiloxane diamine in a suitable organic solvent as an adhesive for making composite materials. In U.S. Patent 3,325,450, the same material is described as a dielectric coating for wire products.
According to one aspect, the present invention provides a semiconductor element for electrical application, comprising a body of semiconductor material having a pair of conductive electrodes, and a protective layer covering a portion of the body, the protective layer being a polyimide-siloxane copolymer material which has recurring structural units of the formula:
wherein: R is a divalent hydrocarbon radical; R' is a monovalent hydrocarbon radical; R" is a tetravalent organic radical which is the residue of a tetracarboxylic acid anhydride; Q is a divalent silicon-free organic radical which is the residue of an organic diamine; x is an integer having a value of 14, m is an integer grater than 1, and n is an integer greater than 1 and the integers designated as m and n are such that the mol per cent of m is equal to 5-50% of the polymer.
According to another aspect, the invention provides a semiconductor element for electrical application comprising: (a) a body of monocrystalline semiconductor material having a pair of conductive electrodes, and (b) a protective layer covering a portion of said body, the protective coating material being a polyimide-siloxane copolymer.
According to a further aspect, the invention provides a semiconductor assembly comprising: (a) a semiconductor element including a body of semiconductor material having at least two regions of one and the opposite conductivity type defining a P-N junction therebetween, said element also including at least two electrodes coupled to said bodv, and a protective layer covering a portion of said element, the protective layer being a polyimide siloxane copolymer.
In application to transistor devices, the protective layer may cover the semiconductor body, including exposed Junctions and any metallizations or surface oxides present. In such an application, the layer provides additional passivation and protects the semiconductor element from physical abrasion, In greater thickness, the material may be used to coat the main blocking junctions of high voltage switching devices for passivation and for protection against voltage breakdown at the surface.
The material may be used as a general encapsulant for semiconductor elements.
The invention will be further described, by way of example only, by reference to the following description and accompanying drawings in which: Figure 1 is a side elevation view in crosssection of a semiconductor element forming a portion of a transistor, and having a protective layer for passivation of the upper surface; Figure 2 is a side elevation view in crosssection of a semiconductor element forming a portion of a high voltage thyristor, and having a protective layer on its edge or "bevel" for passivation and preventing surface breakdown.
Figure 3 is a side elevation view in crosssection of a semiconductor element forming a portion of a medium voltage thyristor, having a circular groove on the face across which the voltage appears, the groove being filled with a protective layer to prevent voltage breakdown, and Figure 4 is a view in perspective of a transistor incorporating a semi-conductor element and a "header" assembly, which is encapsulated with a protective layer to provide mechanical support and passivation functions.
With reference to Figure 1 there is shown a semiconductor element 10 forming a portion of a transistor to the upper surface of which a protective layer is applied. The element 10, or "pellet" as it is sometimes called, is formed of a thin wafer-like semiconductor "chip", typically of silicon (.006x.060x.080 inches), to which flying leads 11 and 12 for external electrical connection are attached. The pellet is typically bonded on its undersurface to a support member (such as is shown in Figure 4) providing for both external electrical connection and mechanical support. The flying leads 11 and 12 are electrically connected to the more substantial external leads (such as are shown in Figure 4), which external leads are supported in a package such as a "TO" can or encapsulated in epoxy.
The semiconductor element 10, as a portion of a junction transistor, has its semiconductor body divided into thee bounded regions. 13, 14, 15 of distinctive conductivities and each of which is electroded by the metallizations at 16, 17 and 18. respectively. The region 15 forming the collector is of N type conductivity, retaining the doping of the original semiconductor material. Electrical contact to the collector is made by the surface metallization 18. The region 14, forming the base, is of P type conductivity. It is formed by diffusion into the original semiconductor material. Its surface metallization, which is shown at 17, takes the form of a ring to which the flying lead 11 is "ball" bonded. The third region 13, forming the emitter, is of N type conductivity. It is formed bv a second diffusion taken part way into the base diffusion. The emitter has a surface metallization 16, to which the flying lead 12 is "ball" bonded.
Three additional insulating and passivating layers 20, 21 and 22 coat the upper surface of the semiconductor element. As so far described, the upper surface of the semiconductor element has the two metallizations 16 and 17. The emitter metallization 16 is substantially coextensive with the emitter region and is confined within it, stopping just short of the emitter-base junction. The emitter-base junction emerges at the top surface of the semiconductor element, where it is covered by a thin insulating and passivating layer (20) of SiO2. The SiO2 layer 20 covers a narrow band to either side of the exposed edge of the emitter base junction on the top surface of the semiconductor element and separates the emitter metallization 16 from the base metallization 17. The base metallization is substantially coextensive with the base region, and is confined within it, stopping just short of the emerging emitter-base junction on the one hand the emerging base collector junction on the other hand. A second layer 21 of SiO2 covers a narrow band to either side of the exposed edge of the base collector junction on the top surface of the semiconductor element.
The SiO2 layers 20, 21 are well known and their positioning over the exposed edge of the two junctions of the transistor perform the function of insulating the two metallizations from one another and from the non-contacted regions and of "passivatinp" the most critical regions on the transistor surface. Customarily, the SiO2 is initially applied over the total top surface.
in which case the SiO2 layer 21 in the finished device may cover not only the exposed junction region but the margin beyond the perimeter of the outer junction.
The entire upper surface of the semiconductor element is then provided uith a final protective layer 22 of the polyimide-siloxane copolymer. The layer 22 is normally applied after the flying leads 11 and 12 are attached. The layer coats both any raw silicon on the surface not previously covered, the SiO2 layers 20, 21 and the surface metallizations 16 and 17. The layer typically has a thickness of about .004 inch The protective laver 22 is formed on the surface of the semiconductor element in the following manner. The initial materials are in liquid form, wherein the polymer precursor materials or the final polymer are dissolved in a suitable solvent. The percentage of solute (dissolved solids) to solvent is selected in respect to the ultimate thickness of the protective layer that is sought and the most convenient mode of application. For the use indicated in the Figure 1 embodiment, where a thickness of about .004 inch is desired. a convenient mode of application is by means of a syringe of typically 0.015 inch needle bore. The liquid solution is manually applied while the applicator observes the coating process through a low power microscope. The syringe is pressed to dispense the liquid, and its spread over the surface of the chip is observed. The presence of too little liquid to cover the surface of the chip is thus avoided.
and any excess has no harmful consequence. The liquid in this case is selfleveling, and since it wets all the contacted surfaces, the subsequent orientation of the chip (vertical or horizontal) prior to solidification is of no concern. The control of the ultimate thickness of the layer using this mode of application is primarily the viscosity of the liquid and the per cent of solids it contains. In such application a typical solution contains about 30% by weight solids (or resinous material).
After application, the applied liquid is heated in a multi-step procedure. The first step is used to drive off the solvent. Where the polymer precursor is employed, the final step is used to complete the polymerization of the precursor materials to form the final polyimide-siloxane copolymer. The firing cycle (using precursor materials) is typically at 135"C in an N2 atmosphere for 30 minutes (or more), at 185"C in an N2 atmosphere for 30 minutes (or more), and finally at 225"C for three hours (or more) in a vacuum. The thickness of the foregoing layer is not critical but has been found to be beneficial in layers as thin as micron. When such thin layers are desired, A continuous layer may be formed bv reducing the viscosity of the solvent to 2 to 40, weight per cent of solids.
After the surface is wetted, it may be subjected to a spinning process to remove the excess and to reduce it to the desired thickness.
In the foregoing embodiment, where the protective polyimide-siloxane layer is from a micron to several thousandths of an inch.
the function of the protective layer is that of passivation. Passivation is commonlv defined to mean rendering a semiconductor device inert or immune to external influences. The polyimide-siloxane layer adheres with great intimacy to the materials which are present on the top surface of the semiconductor. These layers include small areas of semiconductor along the edges of which no SiO2 is applied (but which normally contains some "residual" oxide) to the SiO2 layer, to the electrode metallizations or pads, and finally, to the ball bonds which are applied on the metallizations. The polyimide-siloxane material adheres to each of these materials and creats an interface with these materials of such intimacy that the passage of mobile ions along the interface is precluded, thus preventing slow deterioration of the device parameters. The polyimide siloxane layer is substantially impervious to humidity, and no change in properties of transistor devices has been observed with prolonged exposure to boiling water. The protective layer is highly impervious to small ion migration such as sodium, hydrogen or other negative ions from environmental sources, or from the material itself, which are frequent causes of transistor failure. The polyimidesiloxane layer is a high quality dielectric.
The layer displaces surface charges on the air surface further away from the silicon surface and reduces the formation of induced conduction channels at the surface of the semiconductor. Finally, the polyimide-siloxane material, since it does adhere well to vapor deposited gold, a common constituent of flying leads, as well as to other common metals used for this purpose, strengthens the bond at the electrode metallization. The improvement in strength is often by a factor of 10 to 100.
The foregoing polyimide-siloxane layer thus completes the passivation of a silicon transistor in which SiO2 is the underlayer, and precludes the need for further passivation. One may then complete the packaging of the device by potting it in epoxy, or other relatively less "inert" materials.
The polyimide-siloxane material performs the passivation functions enumerated above over an extremely wide range of temperatures, and is immune to adverse changes in physical properties related to temperature over a range of from -200"C to +4000 C.
A polyimide-siloxane material meeting the aforesaid requirements is the reaction product of a silicon-free organic diamine, an organic tetracarboxylic acid dianhydride and a polysiloxane diamine which is a polymer precursor soluble in a suitable organic solvent. On curing, it yields a copolymer having recurring structural units of the formula:
wherein R is a divalent hydrocarbon radical; R' is a monvalent hydrocarbon radical; R" is a tetravalent organic radical which is the residue of tetracarboxylic acid anhydride; Q is a divalent silicon-free organic radical which is the residue of an organic diamine: x is an integer having a value of I4: m and n are different integers greater than 1, and such that the mol per cent of m is equal to 5--509 of the polymer.
The above-mentioned block copolymers can be prepared by effecting reaction, in the proper molar proportions, of a mixture of ingredients comprising a diaminesiloxane of the general formula:
a silicon-free diamine compound of the formula: Ill NH2 Q NH2 and a tetracarboxylic acid dianhydride having the formula:
wherein R, R', R", Q and x have the meanings given above.
The ultimate polyimide-siloxane composition will consist essentially of the imido structures found in Formulas I and II.
However, the actual precursor materials resulting from the reaction of the diamino siloxane, the silicon-free organic diamine and the tetracarboxylic acid dianhydride will initially be in the form of a polyamic acid structure composed of structural units of the formulas:
where R, R', R", Q, x, m and n have the meanings given above.
The diamine siloxanes of Formula II which may be used in the practice of the present invention include compounds having the following formulas:
and the like.
The diamines of Formula III above are described in the prior art and are to a large extent commercially available materials.
Typical of such diamines from which the prepolymer may be prepared are the following: m-phenylenediamine: p-phenylenediamine: 4,4'-diaminodiphenylpropane: 4,4'-diaminodiphenylmethane benzidine: (hereinafter referred to as "methylenedianiline") 4,4'-diaminodiphenyl sulfide; 4,4'-diaminodiphenyl sulfone: 4,4'diaminodiphenyl ether: I ,5-diaminophthalene: 3,3'-diamethylbenzidine: 3,3'-dimethoxybenzidine: 2,4-bis ( -amino-t-butyl) toluene: bis (p-p-amino-t-butylphenyl)ether; bis (p- -methyl-o-aminopentyl)benzene; 1 ,3-diamino-4-isopropylbenzene: I ,2-bis(3-aminopropoxy)ethane; m-xylylenediamine; p-xylylenediamine; bis(4-aminocyclohexyl)methane; decamethylenediamine; 3-methylheptamethylenediamine; 4,4-dimethylheptamethylenediamine; 2,1 l-dodecanediamine; 2,2-dimethylpropylenediamine; octamethylenediamine; 3-methoxyhexamethylenediamine: 2,5-dimethylhexamethylenediamine; 2,5-dimethylheptamethylenediamine: 3-methylheptamethylenediamine; 5-methylnonamethylenediamine: 1 4-cyclohexanediamine; 1,1 2-octadecanediamine; bis(3-aminopropyl)sulfide: N-methyl-bis(3-aminopropyl)amine; hexamethylenediamine; heptamethylenediamine: nonamethylenediamine; and mixtures thereof. It should be noted that these diamines are given merely for the purpose of illustration and are not considered to be all-inclusive. Other diamines not mentioned will readily be apparent to those skilled in the art.
In the tetracarboxylic acid dianhydrides of Formula IV, the R" is a tetravalent radical, e.g., a radical derived from or containing an aromatic group containing at least 6 carbon atoms characterized by benzonoid unsaturation, wherein each of the 4 carbonyl groups of the dianhydride are attached to a separate carbon atom in the tetravalent radical, the carbonyl groups being in pairs in which the groups in each pair are attached to adjacent carbon atoms of the R radical or to carbon atoms in the R radical at most one carbon atom removed, to provide a 5-membered or 6-membered ring as follows:
Illustrations of dianhydrides suitable for use in the present invention (with their reference designation in parenthesis) include; pyromellitic dianhydride (PMDA): 2,3,6,7-napthalene tetracarboxylic dianhydride; 3,3',4,4'-diphenyl tetracarboxylic dianhydride; 1,2,5,6-napthalene tetracarboxylic dianhydride; 2,2',3,3'-diphenyl tetracarboxylic dianhydride; 2,2-bis(3,4-dicarboxyphenyl) propane dianhydride; bis(3,4-dicarboxyphenyl)sulfone dianhydride; 2,2 - bis[4 - 3,4 - dicarboxyphenoxy) phenyl]propane dianhydride (B PA dianhydride) 2,2-bis[4-(2,3-dicarboxyphenoxy) phenyl]propane dianhydride; benzophenone tetracarboxylic acid dianhydride (BPDA); perylene-l ,2,7,8-tetracarboxylic acid dianhydride; bis(3 ,4-dicarboxyphenyl)ether dianhydride, and bis(3 ,4-dicarboxyphenyl)methane dianhydride; and aliphatic anhydrides such as cyclopentane- tetracarboxylic dianhydride, cyclohexane tetracarboxylic dianhydride, butane tetracarboxylic dianhydride, etc.
Application of the block copolymers or blends of polymers in a suitable solvent (including, for example N-methyl-2pyrrolidone, N,N-diamethylacetamine, N,N-dimethylformamide, etc.) alone or combined with non-solvents to the substrate material may be by conventional means such as dipping, spraying, painting, spinning, etc. The block copolymers may be dried in an initial heating step at temperatures of about 75 to 1500C for a sufficient time frequently under vacuum to remove the solvent. The polyimide acid is then converted to the corresponding polyimide-siloxane by heating at temperatures of about 1500 to 3000C for a sufficient time to effect the desired conversion to the polyimide structure and final cure.
A preferred curing cycle for materials of the above general formula is as follows: (a) from 15 to 30 minutes of from 135"C to 150"C in dry N2 (b) from 15 to 60 minutes at about 185"C+10"C in dry N2 (c) from 1 to 3 hours at about 225"C in vacuum.
Alternatively, it has been found that one may be able to cure the coating material in other atmospheres such, for example, as air for ease of commercial application of this invention.
In particular, a solution of the polymer precursor in the form of polyamic acid form dissolved in N-methyl pyrrolidone containing 25n e solids by weight is prepared in the following manner: A reaction flask flushed by nitrogen is charged with the following chemical ingredients: 401.25 grams N-methyl-2-pyrrolidone 18.6 grams 1,3 bis(a-aminopropyl)tetramethyldisiloxane 34.65 grams methylenedianiline The reaction mixture is stirred until a homogeneous mixture is reasonably assured. To the mixture 80.50 grams of benzophenone tetracarboxylic acid dianhydride is added while the mixture is stirred continuously. Stirring is continued for a period of about 5 hours to obtain a homogeneous fluid. The fluid is very resinous and the length of time of stirring assures completion of the reaction of the chemical constituents therein.
Sufficient material is applied to the semiconductor device in the Figure 1 embodiment to provide a layer whose thickness is from I micron to 100 microns.
When used as an overcoating of oxide passivated devices as in the first embodiment, the minimum thickness provides additional spatial isolation between surface ion contamination and the underlying p-n junction. When applied over unoxided silicon, the minimum thickness is determined by the requirement that the protective layer prevent the penetration of the ambient moisture and sodium ion contamination to the silicon and in order to afford the surface good protection from damage by abrasive action.
It is desirable that the materials of the coating be applied to the surface as a precursor. The precursor consists of resinous material in a suitable solvent. It has been found that a precursor wherein from 10 percent to 40 percent solids by weight are contained therein is suitable for semiconductor work. Preferably, the precursor has from 20 to 40 percent solid resinous material contained therein.
A second embodiment of the invention is shown in Figure 2. In Figure 2, a semiconductor element 30 is shown forming a portion of a high voltage, high power thyristor whose exposed junction regions are protected by a polyimide-siloxane layer.
More particularly the device is a silicon controlled rectifier. The semiconductor element includes a semiconductor body 31 bonded to a thin tungsten expansion plate 32. The semiconductor body is formed of a thin wafer-like chip of silicon. typically in a circular form of 0.420" diameter by .018" in thickness. The semiconductor body has a metallization (not shown) on its undersurface for electrical contact and to promote adhesion by hard soldering to the tungsten expansion plate. To avoid high voltage breakdown, the outer edge of the semiconductor body is provided with a double bevel which is coated with a novel protective layer of polyimide-siloxane.
The semiconductor body of the semiconductor element 30 is divided into four bounded regions 33, 34, 35 and 36 of respectively N, P, N, P conductivity types.
The regions 33, 34 and 36 are electroded and form the cathode, gate and anode regions, respectively. The unelectroded region 35 is an "N" region retaining the doping of the original semiconductor material. The region 35 remains after doping has been carried out from both the top and the bottom surface of the semiconductor body. It is of uniform thickness and continues to the lateral edges of the semiconductor body, where it is exposed.
The region 36, forming the "P" anode region, is formed by diffusion into the undersurface of the semiconductor body. It is of uniform thickness, continuing to the lateral edges of the semiconductor body, where it is exposed. The undersurface of the anode region is electroded, as previously noted, for external electrical connection, mechanical bonding and heat removal. The upper surface of the anode region, where it meets the undersurface of the "N" region, forms a first junction 37, which emerges in a continuous line along the lateral edges of the semiconductor body.
The gate (34) and cathode (33) regions are at the top of the semiconductor body. The gate region (34) is the next region above the nonelectroded region 35 and it is formed by a P diffusion into the upper surface of the semiconductor body. This diffusion is frequently simultaneous with the diffusion forming the region 36. The gate region 34 extends to the lateral edges of the semiconductor body. The undersurface of 34 and the upper surface of the "N" region 35 form a second junction 38, emerging in a second continuous line along the lateral edges of the semiconductor body. The cathode region 33 is a washer shaped "N" diffusion covering the major portion of the upper surface of the chip. It is formed by another diffusion, carried part way into the underlying P gate region. At the same time the gate region 34 extend upwardly to the top surface of the semiconductor body in the center of the semiconductor body and at its perimeter. The boundary between the cathode and gate forms a third junction 40.
In the illustration. the third junction does not reach the lateral edges of the body but emerges on the top surface of the semiconductor body in the form of two concentric rings. The gate metallization 39 is a small circular disc applied at the center of the semiconductor body and contacts the "P" region reaching to the top of the body at the center of the body. The washer shaped cathode metallization surrounding the gate metallization is as shown at 41. It is applied so as to stay within the two concentric rings bounding the washer shaped cathode region. The emerging edges of the third junction are thus on the top surface of the semiconductor bodv.
In the foregoing "SCR" type thyristor, the semiconductor body is designed to be placed in a compression mounted package, wherein the electrical contacts are maintained by compression exerted by the container upon the semiconductor body at its three electroded surfaces.
The upper surface of the semiconductor body is provided with the conventional SiO2 passivation layers which sh that high reverse potentials periodically occur. The danger of surface breakdown at these junctions is reduced by such measures as double beveling the lateral edges.
Additional protection from breakdown is provided if the lateral edges are then coated with the layer 42 in accordance with the invention.
The protective layer 42 is a polyimide siloxane copolymer as previously described.
Since the coating should be formed in a single application, either by brushing or by a syringe, a solution of 40-50 weight per cent by weight solids is desirable. A solution of this concentration has greater viscosity than the lesser concentration mentioned in the prior embodiment. When applied in adequate quantity. the coating is selfleveling. producing a layer whose thickness is in rough proportion to the viscosity of the starting material.
Polvimide siloxane coating has been found to have excellent adhesion to the exposed silicon at the "bevel" of the SCR device, and to provide all the "passivation" functions which are normally required at this point. In addition to preventing device deterioration from the migration of mobile ions to the junction region, or from water vapor, the material has an excellent dielectric strength and a large dielectric constant ( > 3.) In the foregoing application, the polyimide material is suitable for direct adhesion to the semiconductor surfaces around the main blocking junctions. Its high dielectric strength resists surface breakdown of the junction and protects the device even at elevated temperatures on the order of 400"C. The inertness of the polyimide-siloxane material is such that the material does not enter into the conduction phenomena in the normal resistivity encountered for SCR devices.
A protective polyimide-siloxane layer of medium thickness is also of value in semiconductor devices of intermediate voltage. A medium voltage SCR device 50 is shown in Figure 3. It is a center gate SCR device electrically similar to the Figure 2 device. The finished device has four regions 51, 52, 53 and 54 of, respectively, P,N,P,N conductivities, The unelectroded N region 52, totally surrounded by a P region, is the starting material of the semiconductor body. The P diffusion is carried out from top and bottom so as to surround the region 52.
At the edges of the (finished) body, the P diffusions are carried through until they meet. (This diffusion is normally carried out before individual devices are separated). In the center of the body, the diffusion is carried out from the top and from the bottom faces part way into the semiconductor body but stopping well short of eliminating the center N region. The upper P diffusion forms the gate diffusion 53 and the diffusion at the bottom forms the anode diffusion 51. A last N diffusion for the cathode is carried out part way into the upper gate region 53. Due to the P region on the side of the pellet, the anode and cathode diffusions are electrically separated only by a narrow groove 55 formed into the top surface of the semiconductor body which extends down through the P region into the nonelectroded N region (52). The gate metallization is shown at 56 and the cathode metallization is shown at 57.
The passivation requirements of the device 50 are generally similar to those of the high voltage device (30 of Figure 2). The device 50 is normally provided with a shorted emitter so that the other two junctions are the main blocking junctions.
The anode junction, the first main blocking junction, is internal to the semiconductor body except where it emerges in the groove 55. The junction between the gate region 53 and the non-electroded N region 52, the second main blocking junction, is also internal to the device except where it emerges in the groove 55. The junction between the cathode and gate regions emerges on the top surface of the semiconductor body and, as indicated, is generally shorted. The passivation of the top surface of the body 50 is carried out in the same manner as explained in connection with Figure 2. In accordance with the invention, the groove 55 is filled with a polyimide siloxane layer to protect both main blocking junctions.
The groove 55 in the figure 3 embodiment may be partially filled with glass and covered with the polyimide-siloxane herein described, or may be completely filled with the silicone-polyimide. In this embodiment, the silicon polyimide solution is of high viscosity, typically from 35 to 45 weight per cent resinous solids.
The fourth embodiment in which the protective polyimide siloxane material is used as an encapsulant for a semiconductor device is shown in Figure 4. In this embodiment a transistor similar to that shown in Figure 1 is installed on a "header", and the whole is encapsulated in polyimidesiloxane material. The semiconductor chip is shown at 61, and the header is shown at 62. Supporting leads 63, 64, 65 are for the collector, base and emitter, respectively.
The collector lead 63 is bonded to the under surface of the header, which is conductive, while the emitter lead 64 and the base lead 65 are supported in insulating glass seals in the header. The semiconductor chip 61 is attached through its collector metallization to the top surface of the header and bonded flying leads 66 and 67 internally attache the emitter and base metallizations of the chip to the external leads 64 and 65. In accordance with the invention, the assembly, and in particular the upper and lateral surface of the chip 61 and the flying leads 66 and 67 are coated, by dipping in a relatively viscous solution of polyimidesiloxane. If the device is to be completed by a further epoxy casing, the whole upper surface of the header, including the glass to metal seals and the leads 66 and 67, may be coated with the polyimide-siloxane, to which the epoxy, which is cheaper, will readily adhere. If a metal top hat is to be added, the surfaces around the perimeter of the header are left clear for forming the bond.
As mentioned before, in addition to completing the passivation process of the semiconductor, the polyimide-siloxane surface layer in the Figure 4 embodiment considerably strengthens the semiconductor assembly. In particular, the flying leads are more rigid, and are attached more firmly to the chip by virtue of the silicone polyimide encapsulation.
The polyimide-siloxane surface layer is beneficial for coating semiconductor surfaces, whether on bipolar transistors or on field effect transistors. The coating further displaces charges from the surface and helps to prevent the formation of induced channels near such surfaces that would adversely affect the operation of the device.
The thickness of the protective polyimide-siloxane layer depends upon the application. As so far described, the protective layer may be applied directly to a semiconductor body of silicon or other semiconductor material. It may be applied either upon emergent junction regions or at non-junction regions. It may also be applied to surfaces already partially passivated as from an SiO2 coating. In both applications, assuming that the device is not operated at high potentials, the thickness of the polyimide-siloxane layer may be from 1-100 microns. Once the layer has become continuous, the benefits begin to accrue starting at the minimum thickness noted.
When exposed junctions of high voltage devices are coated, then the layer may be thicker-typically from 100 to 750 microns.
In any case, when used as a passivant, the thickness of the layer should be in the range + to 750 microns. When the layer is used as an encapsulant, the upper limit is set primarily by the curing properties of the layer, and the time that may be economically allowed for expelling solvent and completing the cure of the polymer precursors. As an encapsulant, the greater the thickness, the greater the ruggedness of the finished device. In particular, the encapsulant tends to increase the strength of the bonded contacts.
WHAT WE CLAIM IS: 1. A semiconductor element for electrical application comprising: (a) a body of semiconductor material having a pair of conductive electrodes, (b) a protective layer covering a portion of said body, the protective layer being a polyimide-siloxane copolymer material which has recurring structural units of the formula:
wherein R is a divalent hydrocarbon radical; R' is a monovalent hydrocarbon radical; R" is a tetravalent organic radical which is the residue of tetracarboxylic acid anhydride, Q is a divalent silicon-free organic radical which is the residue of an organic diamine; x is an integer having a value of 1 ": m is an integer greater than 1: and n is an integer greater than 1 and the integers designated as m and n are such that the mol per cent of m is equal to 5-50% of the polymer 2. A semiconductor element as claimed in claim 1 wherein: said semiconductor body includes at least two P-N junctions.
3. A semiconductor element as claimed in claim 2 wherein at least one of the junctions intersects the surface of said body beneath said protective layer.
4. A semiconductor element as claimed in claim 3 wherein: (a) the semiconductor material of said semiconductor body is monocrystalline silicon, (b) a second protective layer of SiO2 material is present on one face of said body at the intersection of one of the junctions with said face, and (c) said covered portion of said semiconductor body includes said second protective layer.
5. A semiconductor element as claimed in claim 3 wherein:
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (17)

**WARNING** start of CLMS field may overlap end of DESC **. to the external leads 64 and 65. In accordance with the invention, the assembly, and in particular the upper and lateral surface of the chip 61 and the flying leads 66 and 67 are coated, by dipping in a relatively viscous solution of polyimidesiloxane. If the device is to be completed by a further epoxy casing, the whole upper surface of the header, including the glass to metal seals and the leads 66 and 67, may be coated with the polyimide-siloxane, to which the epoxy, which is cheaper, will readily adhere. If a metal top hat is to be added, the surfaces around the perimeter of the header are left clear for forming the bond. As mentioned before, in addition to completing the passivation process of the semiconductor, the polyimide-siloxane surface layer in the Figure 4 embodiment considerably strengthens the semiconductor assembly. In particular, the flying leads are more rigid, and are attached more firmly to the chip by virtue of the silicone polyimide encapsulation. The polyimide-siloxane surface layer is beneficial for coating semiconductor surfaces, whether on bipolar transistors or on field effect transistors. The coating further displaces charges from the surface and helps to prevent the formation of induced channels near such surfaces that would adversely affect the operation of the device. The thickness of the protective polyimide-siloxane layer depends upon the application. As so far described, the protective layer may be applied directly to a semiconductor body of silicon or other semiconductor material. It may be applied either upon emergent junction regions or at non-junction regions. It may also be applied to surfaces already partially passivated as from an SiO2 coating. In both applications, assuming that the device is not operated at high potentials, the thickness of the polyimide-siloxane layer may be from 1-100 microns. Once the layer has become continuous, the benefits begin to accrue starting at the minimum thickness noted. When exposed junctions of high voltage devices are coated, then the layer may be thicker-typically from 100 to 750 microns. In any case, when used as a passivant, the thickness of the layer should be in the range + to 750 microns. When the layer is used as an encapsulant, the upper limit is set primarily by the curing properties of the layer, and the time that may be economically allowed for expelling solvent and completing the cure of the polymer precursors. As an encapsulant, the greater the thickness, the greater the ruggedness of the finished device. In particular, the encapsulant tends to increase the strength of the bonded contacts. WHAT WE CLAIM IS:
1. A semiconductor element for electrical application comprising: (a) a body of semiconductor material having a pair of conductive electrodes, (b) a protective layer covering a portion of said body, the protective layer being a polyimide-siloxane copolymer material which has recurring structural units of the formula:
wherein R is a divalent hydrocarbon radical; R' is a monovalent hydrocarbon radical; R" is a tetravalent organic radical which is the residue of tetracarboxylic acid anhydride, Q is a divalent silicon-free organic radical which is the residue of an organic diamine; x is an integer having a value of 1 ": m is an integer greater than 1: and n is an integer greater than 1 and the integers designated as m and n are such that the mol per cent of m is equal to 5-50% of the polymer
2. A semiconductor element as claimed in claim 1 wherein: said semiconductor body includes at least two P-N junctions.
3. A semiconductor element as claimed in claim 2 wherein at least one of the junctions intersects the surface of said body beneath said protective layer.
4. A semiconductor element as claimed in claim 3 wherein: (a) the semiconductor material of said semiconductor body is monocrystalline silicon, (b) a second protective layer of SiO2 material is present on one face of said body at the intersection of one of the junctions with said face, and (c) said covered portion of said semiconductor body includes said second protective layer.
5. A semiconductor element as claimed in claim 3 wherein:
(a) a second protective layer of SiO2 is applied to one face of said body at the intersection of said at least one junction with said face. and (b) said portion of said semiconductor element covered by said protective layer includes said second protective layer and uncoated regions of said semiconductor body.
6. A semiconductor element as claimed in claim 3 wherein: (a) a second protective layer of SiO2 is applied to one face of said body at the intersection of said at least one junction with said face, and (b) said portion of said semiconductor body element covered by said protective layer includes said second protective layer, uncoated regions of said semiconductor body, and said electrodes.
7. A semiconductor element as claimed in claim 1 wherein: (a) said semiconductor body has at least two regions of opposite conductivity type forming a P-N junction; and (b) said covered portion of said semiconductor body includes the intersection of the junction with the surface of said body.
8. A semiconductor element as claimed in claim 1 wherein said protective layer is applied directly to the semiconductor material of said body.
9. A semiconductor element as claimed in claim 7 wherein: (a) said semiconductor body is wafer shaped, designed for high voltage applications, (b) said electrodes include an anode on a first face and a cathode on the opposing face, (c) said junction intersects the edge of said wafer. and (d) wherein said protective layer is applied to the semiconductor material of said body on said edge.
10. A semiconductor element as claimed in claim 9 wherein said protective layer is used as a passivant and is from, to 750 microns in thickness.
11. A semiconductor element as claimed in claim 9 wherein said protective layer is for protection against electrical breakdown at the junction surface and is greater than 100 microns in thickness.
12. A semiconductor element as claimed in claim 7 wherein: (a) said semiconductor element is a high voltage device in which isolation between two regions is achieved by a groove in one surface of said body across which a high potential develops, and wherein (b) said groove is filled with an isolation dielectric material, at least a portion of which is said protective layer material.
13. A semiconductor element as claimed in claim 7 wherein: (a) said semiconductor element is a high voltage device in which isolation between two regions is achieved by a groove in one surface of said body across which a high potential develops, and wherein (b) said groove is filled with said protective layer material.
14. A semiconductor element for electrical application comprising: (a) a body of monocrystalline semiconductor material having a pair of conductive electrodes, and (b) a protective layer covering a portion of said body, the protective coating material being a polyimide-siloxane copolymer.
15. A semiconductor assembly comprising: (a) a semiconductor element including a body of semiconductor material having at least two regions of one and the opposite conductivity type defining a P-N junction therebetween, said element also including at least two electrodes coupled to said body, and a protective layer covering a portion of said element, the protective layer being a polyimide siloxane copolymer.
16. A semiconductor assembly as claimed in claim 15 wherein at least part of said P N junction intersects the surface of said body and said protective layer overlies at least a portion of the junction at said surface.
17. A semiconductor element as claimed in claim 1 substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.
GB52024/76A 1975-12-18 1976-12-14 Polyimide-siloxane copolymer protective coating for semiconductor devices Expired GB1563421A (en)

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