FR3117266B1 - Dispositif électroniques comprenant des liaisons filaires - Google Patents

Dispositif électroniques comprenant des liaisons filaires Download PDF

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Publication number
FR3117266B1
FR3117266B1 FR2012889A FR2012889A FR3117266B1 FR 3117266 B1 FR3117266 B1 FR 3117266B1 FR 2012889 A FR2012889 A FR 2012889A FR 2012889 A FR2012889 A FR 2012889A FR 3117266 B1 FR3117266 B1 FR 3117266B1
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Prior art keywords
conductive
electronic device
wired connections
chip
support
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FR2012889A
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FR3117266A1 (fr
Inventor
Alexandre Ayres
Bertrand Borot
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STMicroelectronics Crolles 2 SAS
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STMicroelectronics Crolles 2 SAS
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Priority to FR2012889A priority Critical patent/FR3117266B1/fr
Priority to US17/543,337 priority patent/US11573260B2/en
Publication of FR3117266A1 publication Critical patent/FR3117266A1/fr
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Publication of FR3117266B1 publication Critical patent/FR3117266B1/fr
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/54—Testing for continuity
    • G—PHYSICS
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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
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    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Dispositif électroniques comprenant des liaisons filaires La présente description concerne un dispositif comprenant : une puce (12) fixée sur un support (14) ; des premiers éléments conducteurs (16) situés sur une première face du support ; des premiers plots conducteurs (24a) situés sur la puce, les plots conducteurs étant reliés aux premiers éléments conducteurs par des fils conducteurs (26) ; et une piste conductrice (32) située sur la puce, reliée à chaque plot conducteur par un circuit interrupteur (36). Figure pour l'abrégé : Fig. 3
FR2012889A 2020-12-09 2020-12-09 Dispositif électroniques comprenant des liaisons filaires Active FR3117266B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR2012889A FR3117266B1 (fr) 2020-12-09 2020-12-09 Dispositif électroniques comprenant des liaisons filaires
US17/543,337 US11573260B2 (en) 2020-12-09 2021-12-06 Electronic device comprising wire links

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2012889 2020-12-09
FR2012889A FR3117266B1 (fr) 2020-12-09 2020-12-09 Dispositif électroniques comprenant des liaisons filaires

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FR3117266A1 FR3117266A1 (fr) 2022-06-10
FR3117266B1 true FR3117266B1 (fr) 2023-10-27

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Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006049324A1 (de) * 2006-10-19 2008-04-30 Austriamicrosystems Ag Halbleiterkörper und Verfahren zum Testen eines Halbleiterkörpers
US8884630B2 (en) * 2009-07-24 2014-11-11 Hewlett-Packard Development Company, L.P. Active pin connection monitoring system and method
US8791582B2 (en) * 2010-07-28 2014-07-29 Freescale Semiconductor, Inc. Integrated circuit package with voltage distributor
FR3023066B1 (fr) * 2014-06-30 2017-10-27 Aledia Dispositif optoelectronique comprenant des diodes electroluminescentes et un circuit de commande
JP6135690B2 (ja) * 2015-02-06 2017-05-31 トヨタ自動車株式会社 半導体チップと、その半導体チップにボンディングされるワイヤの断線検出方法
US9698124B2 (en) * 2015-03-03 2017-07-04 Microsemi Semiconductor Limited Embedded circuit package

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Publication number Publication date
FR3117266A1 (fr) 2022-06-10
US20220178989A1 (en) 2022-06-09
US11573260B2 (en) 2023-02-07

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