FR3111730B1 - Procédé et circuit de protection d’un dispositif de mémoire DRAM de l’effet de martelagede rang - Google Patents

Procédé et circuit de protection d’un dispositif de mémoire DRAM de l’effet de martelagede rang Download PDF

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Publication number
FR3111730B1
FR3111730B1 FR2008742A FR2008742A FR3111730B1 FR 3111730 B1 FR3111730 B1 FR 3111730B1 FR 2008742 A FR2008742 A FR 2008742A FR 2008742 A FR2008742 A FR 2008742A FR 3111730 B1 FR3111730 B1 FR 3111730B1
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Prior art keywords
memory device
rank
protecting
dram memory
hammering effect
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Application number
FR2008742A
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English (en)
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FR3111730A1 (fr
Inventor
Fabrice Devaux
Renaud Ayrignac
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Upmem SAS
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Upmem SAS
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Application filed by Upmem SAS filed Critical Upmem SAS
Priority to PCT/EP2021/064551 priority Critical patent/WO2021259593A1/fr
Priority to KR1020237002647A priority patent/KR20230026496A/ko
Priority to CN202180044218.5A priority patent/CN116018645A/zh
Publication of FR3111730A1 publication Critical patent/FR3111730A1/fr
Application granted granted Critical
Publication of FR3111730B1 publication Critical patent/FR3111730B1/fr
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622—Partial refresh of memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/783—Masking faults in memories by using spares or by reconfiguring using programmable devices with refresh of replacement cells, e.g. in DRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/81—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a hierarchical redundancy scheme

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

L’invention porte sur un procédé de protection d’un dispositif de mémoire DRAM de l’effet de martelage de rang, le dispositif de mémoire comprenant une pluralité de bancs composés de rangs mémoire, le procédé étant mise en œuvre par au moins une logique de prévention configurée pour associer respectivement des sections contiguës de rangs d’un banc à des sous-bancs et pour exécuter, à chaque activation d’un rang d’un sous-banc (b) de la mémoire, une étape d’incrémentation d’un nombre requis de rafraichissement préventif (REFRESH_ACC ; REFRESH_ACC/PARAM_D) du sous-banc (b) à l’aide d’un seuil d’activations (PARAM_D) du sous-banc (b). La logique de prévention est également configurée pour exécuter une séquence de rafraichissement préventif des sous-bancs selon leur nombre requis de rafraichissement préventif. L’invention porte également sur un dispositif de mémoire DRAM ou contrôleur d’une telle mémoire comprenant la logique de prévention de l’effet de martelage de rang. ( Figure 1a )
FR2008742A 2020-06-23 2020-08-27 Procédé et circuit de protection d’un dispositif de mémoire DRAM de l’effet de martelagede rang Active FR3111730B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/EP2021/064551 WO2021259593A1 (fr) 2020-06-23 2021-05-31 Procédé et circuit de protection d'un dispositif de mémoire dram contre l'effet d'attaques répétées
KR1020237002647A KR20230026496A (ko) 2020-06-23 2021-05-31 로우 해머 효과로부터 dram 메모리 소자를 보호하는 방법 및 회로
CN202180044218.5A CN116018645A (zh) 2020-06-23 2021-05-31 用于保护dram存储器装置免受行锤效应的方法和电路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2006541A FR3111731B1 (fr) 2020-06-23 2020-06-23 Procédé et circuit de protection d’un dispositif de mémoire DRAM de l’effet de martelagede rang
FR2006541 2020-06-23

Publications (2)

Publication Number Publication Date
FR3111730A1 FR3111730A1 (fr) 2021-12-24
FR3111730B1 true FR3111730B1 (fr) 2023-06-16

Family

ID=74045279

Family Applications (2)

Application Number Title Priority Date Filing Date
FR2006541A Active FR3111731B1 (fr) 2020-06-23 2020-06-23 Procédé et circuit de protection d’un dispositif de mémoire DRAM de l’effet de martelagede rang
FR2008742A Active FR3111730B1 (fr) 2020-06-23 2020-08-27 Procédé et circuit de protection d’un dispositif de mémoire DRAM de l’effet de martelagede rang

Family Applications Before (1)

Application Number Title Priority Date Filing Date
FR2006541A Active FR3111731B1 (fr) 2020-06-23 2020-06-23 Procédé et circuit de protection d’un dispositif de mémoire DRAM de l’effet de martelagede rang

Country Status (2)

Country Link
US (1) US10885966B1 (fr)
FR (2) FR3111731B1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11361811B2 (en) * 2020-06-23 2022-06-14 Upmem Method and circuit for protecting a DRAM memory device from the row hammer effect
US11809743B2 (en) * 2020-09-21 2023-11-07 Advanced Micro Devices, Inc. Refresh management list for DRAM
US11755235B2 (en) * 2020-11-13 2023-09-12 Ciena Corporation Increasing random access bandwidth of a DDR memory in a counter application
FR3120153B1 (fr) 2021-02-22 2024-02-16 Upmem Dispositif mémoire pourvu de circuits mémoire DRAM agences de manière à minimiser la taille d’un bloc mémoire permettant la gestion de l’effet de martelage de rang
FR3121262A1 (fr) * 2021-03-29 2022-09-30 Upmem Dispositif mémoire et procédé de protection d’un dispositif mémoire de l’effet de martelage d’un rang
FR3121261B1 (fr) * 2021-03-29 2024-03-08 Upmem dispositif mémoire DRAM configuré pour permettre une gestion d’un effet de martelage de rang d’une portée p supérieure ou égale à 2
KR20230051873A (ko) 2021-10-12 2023-04-19 삼성전자주식회사 해머 리프레시 로우 어드레스 검출기, 이를 포함하는 반도체 메모리 장치 및 메모리 모듈
FR3130412B1 (fr) 2021-12-09 2023-12-22 Upmem Dispositif mémoire DRAM mettant un œuvre un mécanisme de gestion du martelage de rang
CN117912512A (zh) * 2022-10-12 2024-04-19 长鑫存储技术有限公司 控制电路

Family Cites Families (13)

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JP2002216471A (ja) * 2001-01-17 2002-08-02 Mitsubishi Electric Corp 半導体記憶装置
US20100195393A1 (en) * 2009-01-30 2010-08-05 Unity Semiconductor Corporation Data storage system with refresh in place
US9299400B2 (en) * 2012-09-28 2016-03-29 Intel Corporation Distributed row hammer tracking
KR102086460B1 (ko) * 2013-06-28 2020-03-10 에스케이하이닉스 주식회사 반도체 장치 및 그의 리프레쉬 방법
US9690505B2 (en) * 2013-09-27 2017-06-27 Hewlett Packard Enterprise Development Lp Refresh row address
KR102399475B1 (ko) * 2015-12-28 2022-05-18 삼성전자주식회사 리프레쉬 콘트롤러 및 이를 포함하는 메모리 장치
FR3066842B1 (fr) 2017-05-24 2019-11-08 Upmem Logique de correction de row hammer pour dram avec processeur integre
KR102308778B1 (ko) * 2017-05-24 2021-10-05 삼성전자주식회사 디스터브 로우를 케어하는 메모리 장치 및 그 동작방법
US10410710B2 (en) * 2017-12-27 2019-09-10 Micron Technology, Inc. Systems and methods for performing row hammer refresh operations in redundant memory
KR102358563B1 (ko) * 2018-05-09 2022-02-04 삼성전자주식회사 로우 해머 핸들링과 함께 리프레쉬 동작을 수행하는 메모리 장치 및 이를 포함하는 메모리 시스템
EP3591565A1 (fr) * 2018-07-04 2020-01-08 Koninklijke Philips N.V. Dispositif de calcul ayant une résistance accrue contre des attaques rowhammer
KR102617016B1 (ko) * 2018-09-17 2023-12-27 삼성전자주식회사 자주 접근되는 어드레스를 검출하는 레지스터 클럭 드라이버를 포함하는 메모리 모듈
CN118197372A (zh) 2018-10-09 2024-06-14 美光科技公司 用于行锤击缓解的方法以及采用所述方法的存储器装置和系统

Also Published As

Publication number Publication date
FR3111731A1 (fr) 2021-12-24
FR3111730A1 (fr) 2021-12-24
US10885966B1 (en) 2021-01-05
FR3111731B1 (fr) 2023-01-06

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