US20210035624A1 - Memory device and row-hammer refresh method thereof - Google Patents
Memory device and row-hammer refresh method thereof Download PDFInfo
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- US20210035624A1 US20210035624A1 US16/528,607 US201916528607A US2021035624A1 US 20210035624 A1 US20210035624 A1 US 20210035624A1 US 201916528607 A US201916528607 A US 201916528607A US 2021035624 A1 US2021035624 A1 US 2021035624A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/783—Masking faults in memories by using spares or by reconfiguring using programmable devices with refresh of replacement cells, e.g. in DRAMs
Definitions
- the disclosure relates to a memory device and a row-hammer refresh method thereof, and more particularly, to a memory device and a row-hammer refresh method thereof which do not need to frequently row-hammer refresh word lines in a redundancy area due to the row hammer phenomenon.
- DRAM dynamic random access memory
- the conventional technique row-hammer refreshes the repeatedly turned-on word line (also referred to as an aggressor word line) to protect the adjacent word lines (also referred to as victim word lines) from the row hammer phenomenon.
- an aggressor word line also referred to as an aggressor word line
- victim word lines adjacent word lines
- a row-hammer address calculator having a larger area is required to calculate the word line addresses of the victim word lines.
- the invention provides a memory device and a row-hammer refresh method thereof, in which word lines for separation are added to a redundancy area to reduce the area of the row-hammer address calculator. Moreover, it is not necessary to frequently row-hammer refresh the word lines of the redundancy area, which thereby reduces the row-hammer refresh current.
- An embodiment of the invention provides a memory device.
- the memory device includes a memory array and a controller.
- the memory array has a plurality of normal areas and a redundancy area adjacent to the normal areas.
- the redundancy area includes a plurality of first word lines and a plurality of second word lines which are alternately arranged.
- the controller is coupled to the memory array.
- the controller is configured to row-hammer refresh the normal areas without row-hammer refreshing the redundancy area.
- An embodiment of the invention provides a row-hammer refresh method adapted for a memory device.
- the memory device includes a memory array and a controller, and the memory array has a plurality of normal areas and a redundancy area adjacent to the normal areas.
- the redundancy area includes a plurality of first word lines and a plurality of second word lines which are alternately arranged, and a quantity of the first word lines is a first quantity.
- the controller is configured to row-hammer refresh the normal areas and the redundancy area.
- the row-hammer refresh method includes, but not limited to, the following steps. A quantity of word lines enabled in the redundancy area is calculated. The quantity of the word lines enabled in the redundancy area is compared with the first quantity.
- the first word lines and the second word lines are row-hammer refreshed.
- the quantity of the word lines enabled in the redundancy area is less than or equal to the first quantity, the first word lines and the second word lines are not row-hammer refreshed.
- the memory device and the row-hammer refresh method thereof can reduce the area of the row-hammer address calculator.
- Word lines for separation are added to the redundancy area to reduce the layout area of the row-hammer address calculator.
- the row-hammer refresh current can be further reduced.
- FIG. 1 is a schematic view showing a memory device according to an embodiment of the invention.
- FIG. 2 is a schematic view showing a layout of word lines in a memory array according to an embodiment of the invention.
- FIG. 3 is a schematic view showing a layout of word lines in a memory array according to another embodiment of the invention.
- FIG. 4 is a flowchart showing a row-hammer refresh method according to an embodiment of the invention.
- FIG. 1 is a schematic view showing a memory device according to an embodiment of the invention.
- a memory device 100 includes a memory array 110 and a controller 120 .
- the memory array 110 includes a plurality of word lines and a plurality of memory cells (not shown) and is configured to store data.
- the invention does not limit the architecture of the memory array.
- the controller 120 is coupled to the memory array 110 , and the controller 120 is configured to access, verify, and row-hammer refresh the memory array 110 .
- the invention does not limit the architecture of the controller.
- the controller 120 includes a row-hammer address calculator 130 .
- the row-hammer address calculator 130 is configured to calculate a word line address in the memory array 110 that is expected to be affected by the row hammer phenomenon and needs row-hammer refreshing.
- the controller 120 row-hammer refreshes the word line in the memory array 110 based on the word line address to prevent the memory cells on the word line from losing the stored data.
- FIG. 2 is a schematic view showing a layout of word lines in a memory array according to an embodiment of the invention.
- the memory array 110 has a normal area 210 and a redundancy area 220 adjacent to the normal area 210 .
- the normal area 210 is adjacent to two sides of the redundancy area 220 , but the invention is not limited thereto.
- the normal area 210 includes a plurality of normal word lines NWL and normal memory cells (not shown).
- the redundancy area 220 includes a plurality of first word lines WL 1 , a plurality of second word lines DWL 2 , and redundancy memory cells (not shown).
- the plurality of first word lines WL 1 and the plurality of second word lines DWL 2 are alternately arranged.
- the second word lines DWL 2 are redundant.
- the quantity of the first word lines WL 1 is a first quantity
- the quantity of the second word lines DWL 2 is a second quantity
- the second quantity is greater than the first quantity. It is noted that since the plurality of second word lines DWL 2 separate the plurality of first word lines WL 1 , the plurality of first word lines WL 1 are not adjacent to each other.
- the word lines adjacent to the boundary between the redundancy area 220 and the normal area 210 are the second word lines DWL 2 .
- the controller 120 is configured to row-hammer refresh the normal area 210 without row-hammer refreshing the redundancy area 220 .
- the plurality of first word lines WL 1 include first word lines WL 1 _ 1 to WL 1 _ 11
- the plurality of second word lines DWL 2 include second word lines DWL 2 _ 1 to DWL 2 _ 13 .
- the quantities of the first word lines WL 1 and the second word lines DWL 2 are only illustrated for the convenience of description of the embodiment, and the quantities are determined by the actual requirements and are not limited in the invention.
- the first word line WL 1 _ 1 is located between the second word lines DWL 2 _ 1 and DWL 2 _ 2
- the first word line WL 1 _ 2 is located between the second word lines DWL 2 _ 2 and DWL 2 _ 3 , and so on.
- the second word lines DWL 2 _ 1 to DWL 2 _ 13 are arranged such that the first word lines WL 1 _ 1 to WL 1 _ 11 are not adjacent to each other. Moreover, the word line at the left boundary in the redundancy area 220 is the second word line DWL 2 _ 1 , and the word line at the right boundary in the redundancy area 220 is the second word line DWL 2 _ 13 .
- the second word lines DWL 2 _ 1 to DWL 2 _ 13 are redundant (i.e., the second word lines DWL 2 _ 1 to DWL 2 _ 13 do not need to be turned on)
- the second word lines DWL 2 _ 1 to DWL 2 _ 13 can separate the row hammer between the first word lines WL 1 _ 1 to WL 1 _ 11 and the row hammer to the normal area 210 , so that it is not necessary to consider the row hammer issue of the first word lines WL 1 _ 1 to WL 1 _ 11 in the redundancy area 220 .
- the row-hammer address calculator 130 in the controller 120 does not need to calculate the word line address that requires row-hammer refreshing in the redundancy area 220 , but only needs to calculate the word line address that requires row-hammer refreshing in the normal area 210 , to enable the controller 120 to row-hammer refresh the word line of the normal area 210 to prevent the row hammer issue in the normal area 210 . Since it is not necessary to calculate the word line address that requires row-hammer refreshing in the redundancy area 220 and it is not necessary to frequently row-hammer refresh the redundancy area 220 , it is possible to save the layout area of the row-hammer address calculator 130 originally provided for the redundancy area 220 and reduce the row-hammer refresh current thereof.
- the controller 120 accesses and row-hammer refreshes the normal memory cells through the plurality of normal word lines NWL.
- the controller 120 determines that any one of the plurality of normal word lines NWL is invalid, the controller 120 disables the invalid normal word line and enables one of the plurality of first word lines WL 1 to replace the invalid normal word line.
- the controller 120 performs data verification and determines that one of the plurality of normal word lines NWL is invalid, the controller turns off the invalid normal word line to prohibit access and turns on the first word line WL 1 _ 1 to replace the invalid normal word line.
- FIG. 3 is a schematic view showing a layout of word lines in a memory array according to another embodiment of the invention.
- the memory array 110 has a normal area 310 and a redundancy area 320 adjacent to the normal area 310 .
- the normal area 310 is adjacent to two sides of the redundancy area 320 , but the invention is not limited thereto.
- the normal area 310 includes a plurality of normal word lines NWL and normal memory cells (not shown).
- the redundancy area 320 includes a plurality of first word lines WL 1 , a plurality of second word lines WL 2 , and redundancy memory cells (not shown).
- the plurality of first word lines WL 1 and the plurality of second word lines WL 2 are alternately arranged.
- the second word lines WL 2 are not redundant.
- the redundancy area 320 may include a non-volatile memory, a laser fuse, or an anti-fuse, but the invention is not limited thereto.
- the quantity of the first word lines WL 1 is a first quantity
- the quantity of the second word lines WL 2 is a second quantity
- the second quantity is greater than the first quantity. It is noted that since the plurality of second word lines WL 2 separate the plurality of first word lines WL 1 , the plurality of first word lines WL 1 are not adjacent to each other.
- the word lines adjacent to the boundary between the redundancy area 320 and the normal area 310 are the second word lines WL 2 .
- the controller 120 is configured to row-hammer refresh the normal area 310 and the redundancy area 320 .
- the plurality of first word lines WL 1 include first word lines WL 1 _ 1 to WL 1 _ 11
- the plurality of second word lines WL 2 include second word lines WL 2 _ 1 to WL 2 _ 13 .
- the quantities of the first word lines WL 1 and the second word lines WL 2 are only illustrated for the convenience of description of the embodiment, and the quantities are determined by the actual requirements and are not limited in the invention.
- the first word line WL 1 _ 1 is located between the second word lines WL 2 _ 1 and WL 2 _ 2
- the first word line WL 1 _ 2 is located between the second word lines WL 2 _ 2 and WL 2 _ 3 , and so on.
- the second word lines WL 2 _ 1 to WL 2 _ 13 are arranged such that the first word lines WL 1 _ 1 to WL 1 _ 11 are not adjacent to each other. Moreover, the word line at the left boundary in the redundancy area 320 is the second word line WL 2 _ 1 , and the word line at the right boundary in the redundancy area 320 is the second word line WL 2 _ 13 .
- the second word lines WL 2 _ 1 to WL 2 _ 13 are not redundant (i.e., the second word lines WL 2 _ 1 to WL 2 _ 13 need to be turned on by the controller 120 ), it is necessary to consider the row hammer issue between the first word lines WL 1 _ 1 to WL 1 _ 11 and the second word lines WL 2 _ 1 to WL 2 _ 13 in the redundancy area 320 .
- the row-hammer address calculator 130 of the controller 120 in addition to calculating the word line address that requires row-hammer refreshing in the normal area 310 , the row-hammer address calculator 130 of the controller 120 also needs to calculate the word line address that requires row-hammer refreshing in the redundancy area 320 , to enable the controller 120 to row-hammer refresh the word line of the normal area 310 and the redundancy area 320 to prevent the row hammer issue.
- the controller 120 when the controller 120 determines that any one of the plurality of normal word lines NWL is invalid, the controller 120 disables the invalid normal word line NWL and enables one of the plurality of first word lines WL 1 or the plurality of second word lines WL 2 to replace the invalid normal word line NWL.
- the priority for the controller 120 to enable the plurality of first word lines WL 1 is higher than the plurality of second word lines WL 2 .
- the controller 120 determines that the quantity of the word lines enabled in the redundancy area 320 is less than or equal to the total quantity (i.e., the first quantity) of the first word lines, the controller 120 does not row-hammer refresh the first word lines WL 1 and the second word lines WL 2 .
- the controller 120 determines that the quantity of the word lines enabled in the redundancy area 320 is greater than the quantity (i.e., the first quantity) of the first word lines, the controller 120 row-hammer refreshes the first word lines WL 1 and the second word lines WL 2 .
- the controller 120 when the controller 120 performs data verification and determines that one of the plurality of normal word lines NWL is invalid, the controller 120 turns off the invalid normal word line (not shown) to forbid access, and prioritizingly turns on one of the first word lines WL 1 _ 1 to WL 1 _ 11 (e.g., turning on the first word line WL 1 _ 1 ) to replace the invalid normal word line.
- the controller 120 may turn on the first word line WL 1 _ 2 to replace the next invalid normal word line, and so on.
- the controller 120 may turn on the second word line WL 2 _ 1 .
- the controller 120 may turn on the second word line WL 2 _ 2 , and so on.
- the controller 120 determines that the quantity of the word lines enabled in the redundancy area 320 is less than or equal to the total quantity (i.e., the first quantity) of the first word lines (e.g., when only the first word line WL 1 _ 1 and the first word line WL 1 _ 2 in the first word lines WL 1 are enabled, the quantity of the enabled word lines is 2, which is less than or equal to the total quantity (i.e., 11 ) of the first word lines WL 1 ), since the first word line WL 1 _ 1 and the first word line WL 1 _ 2 which are enabled in the redundancy area 320 are separated by the second word line WL 2 _ 2 which is not turned on, it is not necessary to consider the row hammer issue. Therefore, the controller 120 does not need to row-hammer refresh the first word lines WL 1 _ 1 to WL 1 _ 11 and the second word lines WL 2 _ 1 to WL 2 _ 13 in the redundancy area 320 .
- the controller 120 determines that the quantity of the word lines enabled in the redundancy area 320 is greater than the total quantity (i.e., the first quantity) of the first word lines (e.g., when the first word lines WL 1 _ 1 to WL 1 _ 11 and the second word lines WL 2 _ 1 to WL 2 _ 2 are all enabled, the quantity of the enabled word lines is 13, which is greater than the total quantity (i.e., 11 ) of the first word lines WL 1 ), since the first word lines WL 1 _ 1 to WL 1 _ 2 and the second word lines WL 2 _ 1 to WL 2 _ 2 in the redundancy area 320 are all enabled and are adjacent to each other, and the enablement of the second word line WL 2 _ 1 also affects the word line of the left normal area, it is necessary to consider the row hammer issue.
- the first word lines WL 1 _ 1 to WL 1 _ 11 and the second word lines WL 2 _ 1 to WL 2 _ 2 are
- the controller 120 needs to row-hammer refresh the first word lines WL 1 _ 1 to WL 1 _ 2 and the second word lines WL 2 _ 1 to WL 2 _ 2 in the redundancy area 320 , or row-hammer refresh all the first word lines WL 1 _ 1 to WL 1 _ 11 and the second word lines WL 2 _ 1 to WL 2 _ 13 in the redundancy area 320 .
- the row-hammer refreshing strategy is determined according to the design requirements, and the invention is not limited thereto.
- the row-hammer address calculator 130 of the controller 120 needs to calculate the word line address that requires row-hammer refreshing in the normal area 310 and the redundancy area 320 , to enable the controller 120 to row-hammer refresh the word line of the normal area 310 and the redundancy area 320 to prevent the row hammer issue.
- the layout area in the row-hammer address calculator 130 originally provided for the redundancy area 320 cannot be saved, but the row-hammer refresh current can still be reduced.
- FIG. 4 is a flowchart showing a row-hammer refresh method according to an embodiment of the invention.
- step S 410 the controller calculates a quantity of the word lines enabled in the redundancy area.
- step S 420 the controller compares the quantity of the word lines enabled in the redundancy area with a first quantity. When the quantity of the word lines enabled in the redundancy area is greater than the first quantity, step S 430 is performed. When the quantity of the word lines enabled in the redundancy area is less than or equal to the first quantity, step S 440 is performed.
- step S 430 when the quantity of the word lines enabled in the redundancy area is greater than the first quantity, the controller row-hammer refreshes the first word lines and the second word lines.
- step S 440 when the quantity of the word lines enabled in the redundancy area is less than or equal to the first quantity, the controller does not row-hammer refresh the first word lines and the second word lines.
- the memory device and the row-hammer refresh method thereof can reduce the area of the row-hammer address calculator.
- Word lines for separation are added to the redundancy area to protect the redundancy area from the row hammer phenomenon, so that it is not necessary to calculate the word line address with row hammer in the redundancy area, and thereby the layout area of the row-hammer address calculator can be reduced.
- the row-hammer refresh current can be further reduced.
- the word lines for separation may be further enabled, and the row-hammer refreshing approach may be adjusted according to the quantity of the word lines enabled in the redundancy area, to reduce the row-hammer refresh current.
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Abstract
A memory device and a row-hammer refresh method thereof are provided. The memory device includes a memory array and a controller. The memory array includes a plurality of normal areas and a redundancy area adjacent to the plurality of normal areas. The redundancy area includes a plurality of first word lines and a plurality of second word lines which are alternately arranged. The controller is configured to row-hammer refresh the plurality of normal areas without row-hammer refreshing the redundancy area.
Description
- The disclosure relates to a memory device and a row-hammer refresh method thereof, and more particularly, to a memory device and a row-hammer refresh method thereof which do not need to frequently row-hammer refresh word lines in a redundancy area due to the row hammer phenomenon.
- When a specific word line in a dynamic random access memory (DRAM) is repeatedly turned on multiple times, the memory cells on the word lines adjacent to the specific word line may lose the stored data due to the cross talk or coupling effect. This interference phenomenon is referred to as the row hammer phenomenon.
- To address the row hammer phenomenon, the conventional technique row-hammer refreshes the repeatedly turned-on word line (also referred to as an aggressor word line) to protect the adjacent word lines (also referred to as victim word lines) from the row hammer phenomenon. However, in some DRAM structures having a high memory cell density, it is complicated to calculate the word line addresses of the victim word lines, so a row-hammer address calculator having a larger area is required to calculate the word line addresses of the victim word lines.
- The invention provides a memory device and a row-hammer refresh method thereof, in which word lines for separation are added to a redundancy area to reduce the area of the row-hammer address calculator. Moreover, it is not necessary to frequently row-hammer refresh the word lines of the redundancy area, which thereby reduces the row-hammer refresh current.
- An embodiment of the invention provides a memory device. The memory device includes a memory array and a controller. The memory array has a plurality of normal areas and a redundancy area adjacent to the normal areas. The redundancy area includes a plurality of first word lines and a plurality of second word lines which are alternately arranged. The controller is coupled to the memory array. The controller is configured to row-hammer refresh the normal areas without row-hammer refreshing the redundancy area.
- An embodiment of the invention provides a row-hammer refresh method adapted for a memory device. The memory device includes a memory array and a controller, and the memory array has a plurality of normal areas and a redundancy area adjacent to the normal areas. The redundancy area includes a plurality of first word lines and a plurality of second word lines which are alternately arranged, and a quantity of the first word lines is a first quantity. The controller is configured to row-hammer refresh the normal areas and the redundancy area. The row-hammer refresh method includes, but not limited to, the following steps. A quantity of word lines enabled in the redundancy area is calculated. The quantity of the word lines enabled in the redundancy area is compared with the first quantity. When the quantity of the word lines enabled in the redundancy area is greater than the first quantity, the first word lines and the second word lines are row-hammer refreshed. When the quantity of the word lines enabled in the redundancy area is less than or equal to the first quantity, the first word lines and the second word lines are not row-hammer refreshed.
- Based on the above, in some embodiments of the invention, the memory device and the row-hammer refresh method thereof can reduce the area of the row-hammer address calculator. Word lines for separation are added to the redundancy area to reduce the layout area of the row-hammer address calculator. Moreover, in the invention, since it is not necessary to frequently row-hammer refresh the word lines of the redundancy area, the row-hammer refresh current can be further reduced.
- To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
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FIG. 1 is a schematic view showing a memory device according to an embodiment of the invention. -
FIG. 2 is a schematic view showing a layout of word lines in a memory array according to an embodiment of the invention. -
FIG. 3 is a schematic view showing a layout of word lines in a memory array according to another embodiment of the invention. -
FIG. 4 is a flowchart showing a row-hammer refresh method according to an embodiment of the invention. -
FIG. 1 is a schematic view showing a memory device according to an embodiment of the invention. Referring toFIG. 1 , amemory device 100 includes amemory array 110 and acontroller 120. Thememory array 110 includes a plurality of word lines and a plurality of memory cells (not shown) and is configured to store data. The invention does not limit the architecture of the memory array. Thecontroller 120 is coupled to thememory array 110, and thecontroller 120 is configured to access, verify, and row-hammer refresh thememory array 110. The invention does not limit the architecture of the controller. Thecontroller 120 includes a row-hammer address calculator 130. The row-hammer address calculator 130 is configured to calculate a word line address in thememory array 110 that is expected to be affected by the row hammer phenomenon and needs row-hammer refreshing. Thecontroller 120 row-hammer refreshes the word line in thememory array 110 based on the word line address to prevent the memory cells on the word line from losing the stored data. -
FIG. 2 is a schematic view showing a layout of word lines in a memory array according to an embodiment of the invention. Referring toFIG. 2 , thememory array 110 has anormal area 210 and aredundancy area 220 adjacent to thenormal area 210. In an embodiment, thenormal area 210 is adjacent to two sides of theredundancy area 220, but the invention is not limited thereto. Thenormal area 210 includes a plurality of normal word lines NWL and normal memory cells (not shown). Theredundancy area 220 includes a plurality of first word lines WL1, a plurality of second word lines DWL2, and redundancy memory cells (not shown). The plurality of first word lines WL1 and the plurality of second word lines DWL2 are alternately arranged. In an embodiment, the second word lines DWL2 are redundant. - In an embodiment, the quantity of the first word lines WL1 is a first quantity, the quantity of the second word lines DWL2 is a second quantity, and the second quantity is greater than the first quantity. It is noted that since the plurality of second word lines DWL2 separate the plurality of first word lines WL1, the plurality of first word lines WL1 are not adjacent to each other. Moreover, in the
redundancy area 220, the word lines adjacent to the boundary between theredundancy area 220 and thenormal area 210 are the second word lines DWL2. In an embodiment, thecontroller 120 is configured to row-hammer refresh thenormal area 210 without row-hammer refreshing theredundancy area 220. - For example, in an embodiment, the plurality of first word lines WL1 include first word lines WL1_1 to WL1_11, the plurality of second word lines DWL2 include second word lines DWL2_1 to DWL2_13. The quantities of the first word lines WL1 and the second word lines DWL2 are only illustrated for the convenience of description of the embodiment, and the quantities are determined by the actual requirements and are not limited in the invention. The first word line WL1_1 is located between the second word lines DWL2_1 and DWL2_2, the first word line WL1_2 is located between the second word lines DWL2_2 and DWL2_3, and so on. Namely, the second word lines DWL2_1 to DWL2_13 are arranged such that the first word lines WL1_1 to WL1_11 are not adjacent to each other. Moreover, the word line at the left boundary in the
redundancy area 220 is the second word line DWL2_1, and the word line at the right boundary in theredundancy area 220 is the second word line DWL2_13. In an embodiment, since the second word lines DWL2_1 to DWL2_13 are redundant (i.e., the second word lines DWL2_1 to DWL2_13 do not need to be turned on), the second word lines DWL2_1 to DWL2_13 can separate the row hammer between the first word lines WL1_1 to WL1_11 and the row hammer to thenormal area 210, so that it is not necessary to consider the row hammer issue of the first word lines WL1_1 to WL1_11 in theredundancy area 220. Accordingly, in this embodiment, the row-hammer address calculator 130 in thecontroller 120 does not need to calculate the word line address that requires row-hammer refreshing in theredundancy area 220, but only needs to calculate the word line address that requires row-hammer refreshing in thenormal area 210, to enable thecontroller 120 to row-hammer refresh the word line of thenormal area 210 to prevent the row hammer issue in thenormal area 210. Since it is not necessary to calculate the word line address that requires row-hammer refreshing in theredundancy area 220 and it is not necessary to frequently row-hammer refresh theredundancy area 220, it is possible to save the layout area of the row-hammer address calculator 130 originally provided for theredundancy area 220 and reduce the row-hammer refresh current thereof. - In a common operation, the
controller 120 accesses and row-hammer refreshes the normal memory cells through the plurality of normal word lines NWL. In an embodiment, when thecontroller 120 determines that any one of the plurality of normal word lines NWL is invalid, thecontroller 120 disables the invalid normal word line and enables one of the plurality of first word lines WL1 to replace the invalid normal word line. For example, when thecontroller 120 performs data verification and determines that one of the plurality of normal word lines NWL is invalid, the controller turns off the invalid normal word line to prohibit access and turns on the first word line WL1_1 to replace the invalid normal word line. -
FIG. 3 is a schematic view showing a layout of word lines in a memory array according to another embodiment of the invention. Referring toFIG. 3 , thememory array 110 has anormal area 310 and aredundancy area 320 adjacent to thenormal area 310. In another embodiment, thenormal area 310 is adjacent to two sides of theredundancy area 320, but the invention is not limited thereto. Thenormal area 310 includes a plurality of normal word lines NWL and normal memory cells (not shown). Theredundancy area 320 includes a plurality of first word lines WL1, a plurality of second word lines WL2, and redundancy memory cells (not shown). The plurality of first word lines WL1 and the plurality of second word lines WL2 are alternately arranged. In another embodiment, the second word lines WL2 are not redundant. - In another embodiment, the
redundancy area 320 may include a non-volatile memory, a laser fuse, or an anti-fuse, but the invention is not limited thereto. - In another embodiment, the quantity of the first word lines WL1 is a first quantity, the quantity of the second word lines WL2 is a second quantity, and the second quantity is greater than the first quantity. It is noted that since the plurality of second word lines WL2 separate the plurality of first word lines WL1, the plurality of first word lines WL1 are not adjacent to each other. Moreover, in the
redundancy area 320, the word lines adjacent to the boundary between theredundancy area 320 and thenormal area 310 are the second word lines WL2. In another embodiment, thecontroller 120 is configured to row-hammer refresh thenormal area 310 and theredundancy area 320. - For example, in another embodiment, the plurality of first word lines WL1 include first word lines WL1_1 to WL1_11, and the plurality of second word lines WL2 include second word lines WL2_1 to WL2_13. The quantities of the first word lines WL1 and the second word lines WL2 are only illustrated for the convenience of description of the embodiment, and the quantities are determined by the actual requirements and are not limited in the invention. The first word line WL1_1 is located between the second word lines WL2_1 and WL2_2, the first word line WL1_2 is located between the second word lines WL2_2 and WL2_3, and so on. Namely, the second word lines WL2_1 to WL2_13 are arranged such that the first word lines WL1_1 to WL1_11 are not adjacent to each other. Moreover, the word line at the left boundary in the
redundancy area 320 is the second word line WL2_1, and the word line at the right boundary in theredundancy area 320 is the second word line WL2_13. In another embodiment, since the second word lines WL2_1 to WL2_13 are not redundant (i.e., the second word lines WL2_1 to WL2_13 need to be turned on by the controller 120), it is necessary to consider the row hammer issue between the first word lines WL1_1 to WL1_11 and the second word lines WL2_1 to WL2_13 in theredundancy area 320. Therefore, in another embodiment, in addition to calculating the word line address that requires row-hammer refreshing in thenormal area 310, the row-hammer address calculator 130 of thecontroller 120 also needs to calculate the word line address that requires row-hammer refreshing in theredundancy area 320, to enable thecontroller 120 to row-hammer refresh the word line of thenormal area 310 and theredundancy area 320 to prevent the row hammer issue. - In another embodiment, when the
controller 120 determines that any one of the plurality of normal word lines NWL is invalid, thecontroller 120 disables the invalid normal word line NWL and enables one of the plurality of first word lines WL1 or the plurality of second word lines WL2 to replace the invalid normal word line NWL. In another embodiment, the priority for thecontroller 120 to enable the plurality of first word lines WL1 is higher than the plurality of second word lines WL2. When thecontroller 120 determines that the quantity of the word lines enabled in theredundancy area 320 is less than or equal to the total quantity (i.e., the first quantity) of the first word lines, thecontroller 120 does not row-hammer refresh the first word lines WL1 and the second word lines WL2. When thecontroller 120 determines that the quantity of the word lines enabled in theredundancy area 320 is greater than the quantity (i.e., the first quantity) of the first word lines, thecontroller 120 row-hammer refreshes the first word lines WL1 and the second word lines WL2. - For example, in another embodiment, when the
controller 120 performs data verification and determines that one of the plurality of normal word lines NWL is invalid, thecontroller 120 turns off the invalid normal word line (not shown) to forbid access, and prioritizingly turns on one of the first word lines WL1_1 to WL1_11 (e.g., turning on the first word line WL1_1) to replace the invalid normal word line. When thecontroller 120 determines that the next normal word line is invalid, thecontroller 120 may turn on the first word line WL1_2 to replace the next invalid normal word line, and so on. When thecontroller 120 determines that the next normal word line is invalid and all the first word lines WL1_1 to WL1_11 in theredundancy area 320 are turned on, thecontroller 120 may turn on the second word line WL2_1. After thecontroller 120 turns on the second word line WL2_1, when thecontroller 120 determines that the next normal word line is invalid and all the first word lines WL1_1 to WL1_11 in theredundancy area 320 are turned on, thecontroller 120 may turn on the second word line WL2_2, and so on. - In another embodiment, when the
controller 120 determines that the quantity of the word lines enabled in theredundancy area 320 is less than or equal to the total quantity (i.e., the first quantity) of the first word lines (e.g., when only the first word line WL1_1 and the first word line WL1_2 in the first word lines WL1 are enabled, the quantity of the enabled word lines is 2, which is less than or equal to the total quantity (i.e., 11) of the first word lines WL1), since the first word line WL1_1 and the first word line WL1_2 which are enabled in theredundancy area 320 are separated by the second word line WL2_2 which is not turned on, it is not necessary to consider the row hammer issue. Therefore, thecontroller 120 does not need to row-hammer refresh the first word lines WL1_1 to WL1_11 and the second word lines WL2_1 to WL2_13 in theredundancy area 320. - In another embodiment, when the
controller 120 determines that the quantity of the word lines enabled in theredundancy area 320 is greater than the total quantity (i.e., the first quantity) of the first word lines (e.g., when the first word lines WL1_1 to WL1_11 and the second word lines WL2_1 to WL2_2 are all enabled, the quantity of the enabled word lines is 13, which is greater than the total quantity (i.e., 11) of the first word lines WL1), since the first word lines WL1_1 to WL1_2 and the second word lines WL2_1 to WL2_2 in theredundancy area 320 are all enabled and are adjacent to each other, and the enablement of the second word line WL2_1 also affects the word line of the left normal area, it is necessary to consider the row hammer issue. Therefore, in another embodiment, thecontroller 120 needs to row-hammer refresh the first word lines WL1_1 to WL1_2 and the second word lines WL2_1 to WL2_2 in theredundancy area 320, or row-hammer refresh all the first word lines WL1_1 to WL1_11 and the second word lines WL2_1 to WL2_13 in theredundancy area 320. The row-hammer refreshing strategy is determined according to the design requirements, and the invention is not limited thereto. Accordingly, in another embodiment, the row-hammer address calculator 130 of thecontroller 120 needs to calculate the word line address that requires row-hammer refreshing in thenormal area 310 and theredundancy area 320, to enable thecontroller 120 to row-hammer refresh the word line of thenormal area 310 and theredundancy area 320 to prevent the row hammer issue. In another embodiment, since it is still necessary to calculate the word line address that requires row-hammer refreshing in theredundancy area 320, the layout area in the row-hammer address calculator 130 originally provided for theredundancy area 320 cannot be saved, but the row-hammer refresh current can still be reduced. -
FIG. 4 is a flowchart showing a row-hammer refresh method according to an embodiment of the invention. In step S410, the controller calculates a quantity of the word lines enabled in the redundancy area. Next, in step S420, the controller compares the quantity of the word lines enabled in the redundancy area with a first quantity. When the quantity of the word lines enabled in the redundancy area is greater than the first quantity, step S430 is performed. When the quantity of the word lines enabled in the redundancy area is less than or equal to the first quantity, step S440 is performed. In step S430, when the quantity of the word lines enabled in the redundancy area is greater than the first quantity, the controller row-hammer refreshes the first word lines and the second word lines. In step S440, when the quantity of the word lines enabled in the redundancy area is less than or equal to the first quantity, the controller does not row-hammer refresh the first word lines and the second word lines. - In summary of the above, in some embodiments of the invention, the memory device and the row-hammer refresh method thereof can reduce the area of the row-hammer address calculator. Word lines for separation are added to the redundancy area to protect the redundancy area from the row hammer phenomenon, so that it is not necessary to calculate the word line address with row hammer in the redundancy area, and thereby the layout area of the row-hammer address calculator can be reduced. Moreover, in the invention, since it is not necessary to frequently row-hammer refresh the word lines of the redundancy area, the row-hammer refresh current can be further reduced. On the other hand, in the invention, the word lines for separation may be further enabled, and the row-hammer refreshing approach may be adjusted according to the quantity of the word lines enabled in the redundancy area, to reduce the row-hammer refresh current.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.
Claims (10)
1. A memory device comprising:
a memory array, having a plurality of normal areas and a redundancy area adjacent to the normal areas, wherein the redundancy area comprises a plurality of first word lines and a plurality of second word lines which are alternately arranged; and
a controller, coupled to the memory array, wherein the controller is configured to row-hammer refresh the normal areas without row-hammer refreshing the redundancy area regardless of a quantity of word lines enabled in the redundancy area.
2. The memory device according to claim 1 , wherein the first word lines are not adjacent to each other, and the second word lines are redundant.
3. The memory device according to claim 1 , wherein the controller comprises a row-hammer address calculator, and the row-hammer address calculator is configured to calculate a word line address that requires row-hammer refreshing in the normal areas.
4. The memory device according to claim 1 , wherein the normal areas comprise a plurality of normal word lines, wherein when the controller determines that a first normal word line in the normal word lines is invalid, the controller disables the first normal word line and enables one of the first word lines.
5. The memory device according to claim 1 , wherein the controller comprises a row-hammer address calculator, and the row-hammer address calculator is configured to calculate a word line address that requires row-hammer refreshing in the normal areas and the redundancy area to enable the controller to row-hammer refresh the normal areas and the redundancy area.
6. The memory device according to claim 1 , wherein the normal areas comprise a plurality of normal word lines, wherein when the controller determines that data of a first normal word line in the normal word lines is invalid, the controller disables the first normal word line and enables one of the first word lines or one of the second word lines.
7. The memory device according to claim 6 , wherein a priority for the controller to enable the first word lines is higher than the second word lines.
8. The memory device according to claim 1 , wherein quantities of the first word lines and the second word lines are respectively a first quantity and a second quantity, and the second quantity is greater than the first quantity.
9. The memory device according to claim 8 , wherein when the controller determines that the quantity of word lines enabled in the redundancy area is greater than the first quantity, the controller row-hammer refreshes the first word lines and the second word lines, and when the controller determines that the quantity of the word lines enabled in the redundancy area is less than or equal to the first quantity, the controller does not row-hammer refresh the first word lines and the second word lines.
10. A row-hammer refresh method adapted for a memory device, wherein the memory device comprises a memory array and a controller, the memory array has a plurality of normal areas and a redundancy area adjacent to the normal areas, the redundancy area comprises a plurality of first word lines and a plurality of second word lines which are alternately arranged, a quantity of the first word lines is a first quantity, and the controller is configured to row-hammer refresh the normal areas and the redundancy area, the row-hammer refresh method comprising:
calculating a quantity of word lines enabled in the redundancy area;
comparing the quantity of the word lines enabled in the redundancy area with the first quantity;
when the quantity of the word lines enabled in the redundancy area is greater than the first quantity, row-hammer refreshing the first word lines and the second word lines; and
when the quantity of the word lines enabled in the redundancy area is less than or equal to the first quantity, not row-hammer refreshing the first word lines and the second word lines.
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US11145350B2 (en) * | 2019-08-01 | 2021-10-12 | Winbond Electronics Corp. | Memory device for refreshing redundancy area word lines, and refresh method thereof |
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KR20140002928A (en) | 2012-06-28 | 2014-01-09 | 에스케이하이닉스 주식회사 | Cell array and memory device including the same |
KR102189533B1 (en) | 2013-12-18 | 2020-12-11 | 에스케이하이닉스 주식회사 | Memory and memory system including the same |
KR20160011483A (en) | 2014-07-22 | 2016-02-01 | 에스케이하이닉스 주식회사 | Memory device |
US9478316B1 (en) | 2016-01-08 | 2016-10-25 | SK Hynix Inc. | Memory device |
US9741421B1 (en) * | 2016-04-05 | 2017-08-22 | Micron Technology, Inc. | Refresh circuitry |
US9799391B1 (en) | 2016-11-21 | 2017-10-24 | Nanya Technology Corporation | Dram circuit, redundant refresh circuit and refresh method |
KR20180064940A (en) * | 2016-12-06 | 2018-06-15 | 삼성전자주식회사 | Memory system performing hammer refresh operation |
TWI615840B (en) | 2017-03-29 | 2018-02-21 | 晶豪科技股份有限公司 | Memory device capable of determining candidate wordline for refresh |
US10410710B2 (en) * | 2017-12-27 | 2019-09-10 | Micron Technology, Inc. | Systems and methods for performing row hammer refresh operations in redundant memory |
US20190237132A1 (en) * | 2018-01-30 | 2019-08-01 | Micron Technology, Inc. | Semiconductor device performing row hammer refresh operation |
US10490250B1 (en) * | 2018-08-14 | 2019-11-26 | Micron Technology, Inc. | Apparatuses for refreshing memory of a semiconductor device |
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