FR3057698B1 - Procede de production d'une tranche collee de silicium et tranche collee de silicium - Google Patents

Procede de production d'une tranche collee de silicium et tranche collee de silicium Download PDF

Info

Publication number
FR3057698B1
FR3057698B1 FR1759557A FR1759557A FR3057698B1 FR 3057698 B1 FR3057698 B1 FR 3057698B1 FR 1759557 A FR1759557 A FR 1759557A FR 1759557 A FR1759557 A FR 1759557A FR 3057698 B1 FR3057698 B1 FR 3057698B1
Authority
FR
France
Prior art keywords
wafer
slice
silicon
silicon glued
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1759557A
Other languages
English (en)
Other versions
FR3057698A1 (fr
Inventor
Yoshihiro Koga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
Original Assignee
Sumco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corp filed Critical Sumco Corp
Publication of FR3057698A1 publication Critical patent/FR3057698A1/fr
Priority to FR1907770A priority Critical patent/FR3083917B1/fr
Application granted granted Critical
Publication of FR3057698B1 publication Critical patent/FR3057698B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)

Abstract

Il est proposé un procédé de production d'une tranche collée de silicium (100) et une tranche collée de silicium (100) qui permettent le maintien d'une capacité de getterisation après que la tranche collée de silicium (100) a été produite et même après que la tranche collée de silicium (100) a subi un autre traitement thermique dans un processus de formation de dispositif ou similaire. Le procédé peut inclure une étape de collage consistant à coller une surface d'une tranche (110) utilisée pour un substrat de support et une surface d'une tranche (120) utilisée pour une couche active (125) selon un procédé de collage sous vide à température normale ; une étape d'amincissement consistant à amincir la tranche (120) utilisée pour la couche active (125) et à convertir la tranche (120) amincie en la couche active (125) ; et une étape de traitement thermique, réalisée après l'étape de collage.
FR1759557A 2016-10-14 2017-10-12 Procede de production d'une tranche collee de silicium et tranche collee de silicium Active FR3057698B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR1907770A FR3083917B1 (fr) 2016-10-14 2019-07-11 Procede de production d’une tranche collee de silicium et tranche collee de silicium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016202756 2016-10-14
JP2016202756A JP6604300B2 (ja) 2016-10-14 2016-10-14 シリコン接合ウェーハの製造方法

Publications (2)

Publication Number Publication Date
FR3057698A1 FR3057698A1 (fr) 2018-04-20
FR3057698B1 true FR3057698B1 (fr) 2021-05-14

Family

ID=61837918

Family Applications (2)

Application Number Title Priority Date Filing Date
FR1759557A Active FR3057698B1 (fr) 2016-10-14 2017-10-12 Procede de production d'une tranche collee de silicium et tranche collee de silicium
FR1907770A Active FR3083917B1 (fr) 2016-10-14 2019-07-11 Procede de production d’une tranche collee de silicium et tranche collee de silicium

Family Applications After (1)

Application Number Title Priority Date Filing Date
FR1907770A Active FR3083917B1 (fr) 2016-10-14 2019-07-11 Procede de production d’une tranche collee de silicium et tranche collee de silicium

Country Status (2)

Country Link
JP (1) JP6604300B2 (fr)
FR (2) FR3057698B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7115297B2 (ja) * 2018-12-25 2022-08-09 株式会社Sumco 多結晶ダイヤモンド自立基板及びその製造方法
JP7424274B2 (ja) 2020-11-11 2024-01-30 株式会社Sumco 貼り合わせウェーハ及び貼り合わせウェーハの製造方法
FR3126169A1 (fr) * 2021-08-12 2023-02-17 Stmicroelectronics (Tours) Sas Procédé de fabrication de composants radiofréquence

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02250329A (ja) * 1989-03-24 1990-10-08 Hitachi Ltd 半導体デバイスおよび張り合わせ基板ならびにその製造方法
JP5667743B2 (ja) * 2008-09-29 2015-02-12 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP6303321B2 (ja) * 2013-08-08 2018-04-04 株式会社Sumco 貼り合わせウェーハの製造方法および貼り合わせウェーハ
JP2015176986A (ja) * 2014-03-14 2015-10-05 京セラ株式会社 複合基板の製造方法

Also Published As

Publication number Publication date
FR3083917B1 (fr) 2022-06-10
FR3057698A1 (fr) 2018-04-20
JP6604300B2 (ja) 2019-11-13
JP2018064057A (ja) 2018-04-19
FR3083917A1 (fr) 2020-01-17

Similar Documents

Publication Publication Date Title
FR3083917B1 (fr) Procede de production d’une tranche collee de silicium et tranche collee de silicium
SG10201805702QA (en) Method of forming an integrated circuit and related integrated circuit
US10811306B2 (en) Preparation method of multilayer monocrystalline silicon film
MY174538A (en) Wafer processing method
SG10201804904YA (en) Wafer producing apparatus
JP2016213490A5 (fr)
CN106611739A (zh) 衬底及其制造方法
FR3036844B1 (fr) Procede de fabrication de semi-conducteur sur isolant
EP2105957A3 (fr) Procédé de fabrication d'un substrat SOI et procédé de fabrication d'un dispositif semi-conducteur
CN103258778B (zh) 带有空腔的衬底的制备方法
GB2541146A (en) Method of manufacturing a germanium-on-insulator substrate
CN105845557B (zh) 实现多晶硅栅极平坦化的方法
WO2010059419A3 (fr) Procédé de formation d'une couche semi-conductrice
US8450185B2 (en) Semiconductor structures having directly bonded diamond heat sinks and methods for making such structures
TWI631626B (zh) 移除處理晶圓
US9111996B2 (en) Semiconductor-on-insulator structure and method of fabricating the same
US11393772B2 (en) Bonding method for semiconductor substrate, and bonded semiconductor substrate
CN103050432A (zh) 一种GaAsOI结构及Ⅲ-ⅤOI结构的制备方法
CN104040686B (zh) 热氧化异种复合基板及其制造方法
US20140308801A1 (en) Anything on Glass
WO2016196216A8 (fr) Procédés pour le traitement de plaquettes à semi-conducteurs ayant une finition polycristalline
WO2015074480A1 (fr) Procédé de préparation de substrat semi-conducteur à bords lisses
FR3053835B1 (fr) Dispositif cascode integre monolithiquement
US10170356B2 (en) SOI substrate and manufacturing method thereof
Kim et al. Plasma dicing before grinding process for highly reliable singulation of low-profile and large die sizes in advanced packages

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7