FR2880160B1 - Module electronique double face pour carte a puce hybride - Google Patents

Module electronique double face pour carte a puce hybride

Info

Publication number
FR2880160B1
FR2880160B1 FR0413951A FR0413951A FR2880160B1 FR 2880160 B1 FR2880160 B1 FR 2880160B1 FR 0413951 A FR0413951 A FR 0413951A FR 0413951 A FR0413951 A FR 0413951A FR 2880160 B1 FR2880160 B1 FR 2880160B1
Authority
FR
France
Prior art keywords
double
electronic module
chip card
hybrid chip
sided electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0413951A
Other languages
English (en)
Other versions
FR2880160A1 (fr
Inventor
Virgile Meireles
Pierre Benato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASK SA
Original Assignee
ASK SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ASK SA filed Critical ASK SA
Priority to FR0413951A priority Critical patent/FR2880160B1/fr
Priority to US11/315,273 priority patent/US20060139901A1/en
Priority to TW094146597A priority patent/TW200634652A/zh
Priority to CNB2005800452807A priority patent/CN100527161C/zh
Priority to EP05850625A priority patent/EP1834352A1/fr
Priority to PCT/FR2005/003293 priority patent/WO2006070140A1/fr
Publication of FR2880160A1 publication Critical patent/FR2880160A1/fr
Application granted granted Critical
Publication of FR2880160B1 publication Critical patent/FR2880160B1/fr
Priority to HK08106738.6A priority patent/HK1116919A1/xx
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
FR0413951A 2004-12-28 2004-12-28 Module electronique double face pour carte a puce hybride Expired - Fee Related FR2880160B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0413951A FR2880160B1 (fr) 2004-12-28 2004-12-28 Module electronique double face pour carte a puce hybride
US11/315,273 US20060139901A1 (en) 2004-12-28 2005-12-23 Double-sided electronic module for hybrid smart card
TW094146597A TW200634652A (en) 2004-12-28 2005-12-27 Double-sided electronic module for hybrid smart card
EP05850625A EP1834352A1 (fr) 2004-12-28 2005-12-28 Module electronique double face pour carte a puce hybride
CNB2005800452807A CN100527161C (zh) 2004-12-28 2005-12-28 用于混合式智能卡的双面电子模块和混合式智能卡
PCT/FR2005/003293 WO2006070140A1 (fr) 2004-12-28 2005-12-28 Module electronique double face pour carte a puce hybride
HK08106738.6A HK1116919A1 (en) 2004-12-28 2008-06-18 Double-sided electronic module for hybrid smart card and hybrid smart card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0413951A FR2880160B1 (fr) 2004-12-28 2004-12-28 Module electronique double face pour carte a puce hybride

Publications (2)

Publication Number Publication Date
FR2880160A1 FR2880160A1 (fr) 2006-06-30
FR2880160B1 true FR2880160B1 (fr) 2007-03-30

Family

ID=34953958

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0413951A Expired - Fee Related FR2880160B1 (fr) 2004-12-28 2004-12-28 Module electronique double face pour carte a puce hybride

Country Status (7)

Country Link
US (1) US20060139901A1 (fr)
EP (1) EP1834352A1 (fr)
CN (1) CN100527161C (fr)
FR (1) FR2880160B1 (fr)
HK (1) HK1116919A1 (fr)
TW (1) TW200634652A (fr)
WO (1) WO2006070140A1 (fr)

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WO2005093645A1 (fr) * 2004-03-25 2005-10-06 Bauer, Eric Procede de fabrication d'une etiquette electronique et etiquette electronique obtenue par ledit procede
KR100723491B1 (ko) * 2005-07-14 2007-05-30 삼성전자주식회사 범용 인쇄 회로 기판 및 이를 사용한 스마트 카드
GB0805780D0 (en) * 2008-03-31 2008-04-30 Royal Bank Of Scotland Plc The Processor card arrangement
FR2936075B1 (fr) * 2008-09-12 2010-12-31 Arjowiggins Licensing Sas Structure comportant au moins deux dispositifs a microcircuit integre a communication sans contact
FR2948796A1 (fr) * 2009-07-28 2011-02-04 Ask Sa Support de dispositif d'identification radiofrequence pour carte hybride et son procede de fabrication
KR101736862B1 (ko) * 2010-06-29 2017-05-17 엘지전자 주식회사 이동 단말기의 케이스, 이를 구비하는 이동 단말기 및 이동 단말기의 케이스 제조 방법
FR2977958A1 (fr) * 2011-07-12 2013-01-18 Ask Sa Carte a circuit integre hybride contact-sans contact a tenue renforcee du module electronique
US8649820B2 (en) 2011-11-07 2014-02-11 Blackberry Limited Universal integrated circuit card apparatus and related methods
USD703208S1 (en) 2012-04-13 2014-04-22 Blackberry Limited UICC apparatus
US8936199B2 (en) 2012-04-13 2015-01-20 Blackberry Limited UICC apparatus and related methods
USD701864S1 (en) * 2012-04-23 2014-04-01 Blackberry Limited UICC apparatus
CN103473593B (zh) * 2012-06-05 2018-10-19 德昌电机(深圳)有限公司 智能卡、智能卡接触垫载板及其制造方法
FR3013504B1 (fr) 2013-11-18 2022-06-10 Interplex Microtech Procede de fabrication d'un support d'une puce electronique, support de puce et ensemble de tels supports
EP2892012A1 (fr) * 2014-01-06 2015-07-08 Gemalto SA Module électronique, son procédé de fabrication, et dispositif électronique comprenant un tel module
US9390365B2 (en) 2014-04-10 2016-07-12 American Banknote Corporation Integrated circuit module for a dual-interface smart card
FR3021145B1 (fr) * 2014-05-14 2018-08-31 Linxens Holding Procede de fabrication d'un circuit pour module de carte a puce et circuit pour module de carte a puce
US9965716B2 (en) 2015-08-14 2018-05-08 Capital One Services, Llc Two-piece transaction card construction
EP3159831B1 (fr) * 2015-10-21 2018-10-03 Nxp B.V. Carte à circuit intégré double interface
CN106935515A (zh) * 2015-12-29 2017-07-07 无锡华润安盛科技有限公司 引线框架及其制造方法、基于该引线框架的芯片封装方法
CN107025481B (zh) * 2016-02-02 2021-08-20 上海伯乐电子有限公司 柔性印制电路板及应用其的智能卡模块和智能卡
FR3049739B1 (fr) * 2016-03-30 2021-03-12 Linxens Holding Procedes de fabrication de cartes a puce et de supports d’antenne pour carte a puce
DE102016106698A1 (de) * 2016-04-12 2017-10-12 Infineon Technologies Ag Chipkarte und Verfahren zum Herstellen einer Chipkarte
FR3051063B1 (fr) * 2016-05-06 2021-02-12 Linxens Holding Procede de fabrication de cartes a puce et carte a puce obtenue par ce procede
FR3063555B1 (fr) * 2017-03-03 2021-07-09 Linxens Holding Carte a puce et procede de fabrication d’une carte a puce
WO2019045638A1 (fr) * 2017-08-28 2019-03-07 Smartflex Technology Pte Ltd Modules de circuit intégré et cartes intelligentes les intégrant
FR3086098B1 (fr) * 2018-09-18 2020-12-04 Smart Packaging Solutions Procede de fabrication d'un module electronique pour objet portatif
FR3086099B1 (fr) * 2018-09-18 2022-12-16 Smart Packaging Solutions Procede de fabrication d'un module a carte et le module obtenu
US11003979B1 (en) * 2019-10-18 2021-05-11 Capital One Service, LLC Multi-faced payment card with partitioned dual smart chips and antennae
CN111626395A (zh) * 2020-05-29 2020-09-04 东信和平科技股份有限公司 一种双界面安全芯片卡及制作方法

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WO2004079647A1 (fr) * 2003-03-06 2004-09-16 Axalto Sa Micromodule a double interface pouvant etre teste sur bobine

Also Published As

Publication number Publication date
HK1116919A1 (en) 2009-01-02
FR2880160A1 (fr) 2006-06-30
CN101095220A (zh) 2007-12-26
EP1834352A1 (fr) 2007-09-19
TW200634652A (en) 2006-10-01
WO2006070140A1 (fr) 2006-07-06
US20060139901A1 (en) 2006-06-29
CN100527161C (zh) 2009-08-12

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Legal Events

Date Code Title Description
GC Lien (pledge) constituted
GC Lien (pledge) constituted

Effective date: 20110608

RG Lien (pledge) cancelled

Effective date: 20140825

GC Lien (pledge) constituted

Effective date: 20151210

ST Notification of lapse

Effective date: 20160831