FR2786633B1 - Procedes et circuits d'entree/sortie de donnees qui inversent selectivement les bits - Google Patents

Procedes et circuits d'entree/sortie de donnees qui inversent selectivement les bits

Info

Publication number
FR2786633B1
FR2786633B1 FR9910401A FR9910401A FR2786633B1 FR 2786633 B1 FR2786633 B1 FR 2786633B1 FR 9910401 A FR9910401 A FR 9910401A FR 9910401 A FR9910401 A FR 9910401A FR 2786633 B1 FR2786633 B1 FR 2786633B1
Authority
FR
France
Prior art keywords
circuits
methods
output
data input
selectively reverse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9910401A
Other languages
English (en)
Other versions
FR2786633A1 (fr
Inventor
Jung Hawn Choi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2786633A1 publication Critical patent/FR2786633A1/fr
Application granted granted Critical
Publication of FR2786633B1 publication Critical patent/FR2786633B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
FR9910401A 1998-08-19 1999-08-11 Procedes et circuits d'entree/sortie de donnees qui inversent selectivement les bits Expired - Fee Related FR2786633B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980033627A KR100272171B1 (ko) 1998-08-19 1998-08-19 저전류 동작 출력 회로 및 입출력 시스템과이를 이용한 데이터입출력 방법

Publications (2)

Publication Number Publication Date
FR2786633A1 FR2786633A1 (fr) 2000-06-02
FR2786633B1 true FR2786633B1 (fr) 2004-09-03

Family

ID=19547634

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9910401A Expired - Fee Related FR2786633B1 (fr) 1998-08-19 1999-08-11 Procedes et circuits d'entree/sortie de donnees qui inversent selectivement les bits

Country Status (7)

Country Link
US (1) US6584572B1 (fr)
JP (1) JP2000099218A (fr)
KR (1) KR100272171B1 (fr)
DE (1) DE19937829A1 (fr)
FR (1) FR2786633B1 (fr)
GB (1) GB2341022B (fr)
TW (1) TW451456B (fr)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6463003B2 (en) 2000-06-07 2002-10-08 Advanced Micro Devices, Inc. Power saving scheme for burst mode implementation during reading of data from a memory device
JP2002108522A (ja) * 2000-09-26 2002-04-12 Internatl Business Mach Corp <Ibm> データ転送装置、表示装置、データ送出装置、データ受取装置、データの転送方法
GB0024226D0 (en) 2000-10-04 2000-11-15 Lsi Logic Corp Improvements in or relating to the reduction of simultaneous switching noise in integrated circuits
US20020156953A1 (en) * 2001-02-28 2002-10-24 Beiley Mark A. Dynamic bus inversion method
US6671212B2 (en) 2002-02-08 2003-12-30 Ati Technologies Inc. Method and apparatus for data inversion in memory device
JP4505195B2 (ja) * 2003-04-01 2010-07-21 エイティアイ テクノロジーズ インコーポレイテッド メモリデバイスにおいてデータを反転させるための方法および装置
KR100546339B1 (ko) * 2003-07-04 2006-01-26 삼성전자주식회사 차동 데이터 스트로빙 모드와 데이터 반전 스킴을 가지는단일 데이터 스트로빙 모드를 선택적으로 구현할 수 있는반도체 장치
JP4492928B2 (ja) * 2003-12-08 2010-06-30 ルネサスエレクトロニクス株式会社 データ伝送装置
US20050132112A1 (en) * 2003-12-10 2005-06-16 Pawlowski J. T. I/O energy reduction using previous bus state and I/O inversion bit for bus inversion
KR100845141B1 (ko) * 2007-01-17 2008-07-10 삼성전자주식회사 싱글 레이트 인터페이스 장치, 듀얼 레이트 인터페이스장치 및 듀얼 레이트 인터페이싱 방법
US9116828B2 (en) 2008-06-11 2015-08-25 Micron Technology, Inc. Data bus inversion usable in a memory system
US8069403B2 (en) * 2008-07-01 2011-11-29 Sandisk Technologies Inc. Majority voting logic circuit for dual bus width
JP5289855B2 (ja) * 2008-08-07 2013-09-11 ルネサスエレクトロニクス株式会社 半導体集積回路
US20110150270A1 (en) * 2009-12-22 2011-06-23 Carpenter Michael D Postal processing including voice training
JP5726425B2 (ja) * 2010-03-04 2015-06-03 エイティアイ テクノロジーズ インコーポレイテッド メモリデバイスにおいてデータを反転させるための方法および装置
TWI618553B (zh) * 2015-04-20 2018-03-21 Protector Sprinkler Ind Co Ltd Valve control device for fire water supply pipeline
JP6670341B2 (ja) 2018-05-25 2020-03-18 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． メモリデバイス及び多数検出器

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3172331D1 (en) 1981-06-25 1985-10-24 Ibm Method and device for transmitting logic signals between micro chips
JPS59212027A (ja) * 1983-05-18 1984-11-30 Toshiba Corp 半導体集積回路の出力回路
US4667337A (en) 1985-08-28 1987-05-19 Westinghouse Electric Corp. Integrated circuit having outputs configured for reduced state changes
JPS6252708A (ja) * 1985-08-30 1987-03-07 Nec Home Electronics Ltd デイジタル磁気記録装置
JPH06111010A (ja) 1992-09-29 1994-04-22 Ricoh Co Ltd Ｄｒａｍ及びコントローラ
JP3346999B2 (ja) 1996-01-08 2002-11-18 株式会社東芝 入出力装置
US6243779B1 (en) * 1996-11-21 2001-06-05 Integrated Device Technology, Inc. Noise reduction system and method for reducing switching noise in an interface to a large width bus
US5874833A (en) * 1997-02-03 1999-02-23 International Business Machines Corporation True/complement output bus for reduced simulataneous switching noise
US5890005A (en) * 1997-06-02 1999-03-30 Nokia Mobile Phones Limited Low power, low interconnect complexity microprocessor and memory interface

Also Published As

Publication number Publication date
FR2786633A1 (fr) 2000-06-02
GB9918763D0 (en) 1999-10-13
KR100272171B1 (ko) 2000-12-01
GB2341022B (en) 2003-07-02
JP2000099218A (ja) 2000-04-07
TW451456B (en) 2001-08-21
KR20000014280A (ko) 2000-03-06
US6584572B1 (en) 2003-06-24
DE19937829A1 (de) 2000-02-24
GB2341022A (en) 2000-03-01

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Effective date: 20110502