FR2754924B1 - Circuit de memoire tampon d'entree/sortie capable de minimiser le transfert de donnees requis dans les operations de tamponnage d'entree et de sortie - Google Patents
Circuit de memoire tampon d'entree/sortie capable de minimiser le transfert de donnees requis dans les operations de tamponnage d'entree et de sortieInfo
- Publication number
- FR2754924B1 FR2754924B1 FR9712009A FR9712009A FR2754924B1 FR 2754924 B1 FR2754924 B1 FR 2754924B1 FR 9712009 A FR9712009 A FR 9712009A FR 9712009 A FR9712009 A FR 9712009A FR 2754924 B1 FR2754924 B1 FR 2754924B1
- Authority
- FR
- France
- Prior art keywords
- input
- output buffer
- minimizing
- data transfer
- memory circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8256807A JP3028932B2 (ja) | 1996-09-27 | 1996-09-27 | 入出力バッファメモリ回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2754924A1 FR2754924A1 (fr) | 1998-04-24 |
FR2754924B1 true FR2754924B1 (fr) | 1999-04-30 |
Family
ID=17297719
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9712009A Expired - Fee Related FR2754924B1 (fr) | 1996-09-27 | 1997-09-26 | Circuit de memoire tampon d'entree/sortie capable de minimiser le transfert de donnees requis dans les operations de tamponnage d'entree et de sortie |
Country Status (4)
Country | Link |
---|---|
US (1) | US5835418A (fr) |
JP (1) | JP3028932B2 (fr) |
DE (1) | DE19742673C2 (fr) |
FR (1) | FR2754924B1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020184381A1 (en) * | 2001-05-30 | 2002-12-05 | Celox Networks, Inc. | Method and apparatus for dynamically controlling data flow on a bi-directional data bus |
EP1316955A1 (fr) * | 2001-11-30 | 2003-06-04 | Infineon Technologies AG | Dispositif de stockage intermédiaire |
US20050065501A1 (en) * | 2003-09-23 | 2005-03-24 | Scimed Life Systems, Inc. | Energy activated vaso-occlusive devices |
ITVA20030052A1 (it) * | 2003-12-23 | 2005-06-24 | St Microelectronics Srl | Metodo e circuito di individuazione di celle di memoria anomale. |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4723226A (en) * | 1982-09-29 | 1988-02-02 | Texas Instruments Incorporated | Video display system using serial/parallel access memories |
US4847812A (en) * | 1986-09-18 | 1989-07-11 | Advanced Micro Devices | FIFO memory device including circuit for generating flag signals |
US5255238A (en) * | 1988-09-08 | 1993-10-19 | Hitachi, Ltd. | First-in first-out semiconductor memory device |
JP2818418B2 (ja) * | 1988-09-08 | 1998-10-30 | 株式会社日立製作所 | 半導体記憶装置 |
JPH0770213B2 (ja) * | 1988-10-03 | 1995-07-31 | 三菱電機株式会社 | 半導体メモリ装置 |
EP0483441B1 (fr) * | 1990-11-02 | 1998-01-14 | STMicroelectronics S.r.l. | Arrangement pour stocker des données à base de FIFO |
JP3435783B2 (ja) * | 1994-03-17 | 2003-08-11 | 株式会社日立製作所 | 複数組のデータバッファを備える記憶素子及び記憶素子を用いたデータ処理システム |
US5490113A (en) * | 1994-06-15 | 1996-02-06 | Digital Equipment Corporation | Memory stream buffer |
-
1996
- 1996-09-27 JP JP8256807A patent/JP3028932B2/ja not_active Expired - Fee Related
-
1997
- 1997-09-26 US US08/938,839 patent/US5835418A/en not_active Expired - Lifetime
- 1997-09-26 DE DE19742673A patent/DE19742673C2/de not_active Expired - Fee Related
- 1997-09-26 FR FR9712009A patent/FR2754924B1/fr not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE19742673C2 (de) | 2003-03-27 |
JP3028932B2 (ja) | 2000-04-04 |
FR2754924A1 (fr) | 1998-04-24 |
DE19742673A1 (de) | 1998-04-02 |
US5835418A (en) | 1998-11-10 |
JPH10106253A (ja) | 1998-04-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |