ITVA20030052A1 - Metodo e circuito di individuazione di celle di memoria anomale. - Google Patents

Metodo e circuito di individuazione di celle di memoria anomale.

Info

Publication number
ITVA20030052A1
ITVA20030052A1 IT000052A ITVA20030052A ITVA20030052A1 IT VA20030052 A1 ITVA20030052 A1 IT VA20030052A1 IT 000052 A IT000052 A IT 000052A IT VA20030052 A ITVA20030052 A IT VA20030052A IT VA20030052 A1 ITVA20030052 A1 IT VA20030052A1
Authority
IT
Italy
Prior art keywords
anomal
identification
circuit
memory cells
cells
Prior art date
Application number
IT000052A
Other languages
English (en)
Inventor
Massimo Bassi
Matteo Patelmo
Rosario Portoghese
Stefano Scuratti
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT000052A priority Critical patent/ITVA20030052A1/it
Priority to US11/022,516 priority patent/US7072239B2/en
Publication of ITVA20030052A1 publication Critical patent/ITVA20030052A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0401—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals in embedded memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0405—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals comprising complete test loop
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current
IT000052A 2003-12-23 2003-12-23 Metodo e circuito di individuazione di celle di memoria anomale. ITVA20030052A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT000052A ITVA20030052A1 (it) 2003-12-23 2003-12-23 Metodo e circuito di individuazione di celle di memoria anomale.
US11/022,516 US7072239B2 (en) 2003-12-23 2004-12-23 Method and circuit for locating anomalous memory cells

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000052A ITVA20030052A1 (it) 2003-12-23 2003-12-23 Metodo e circuito di individuazione di celle di memoria anomale.

Publications (1)

Publication Number Publication Date
ITVA20030052A1 true ITVA20030052A1 (it) 2005-06-24

Family

ID=34803717

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000052A ITVA20030052A1 (it) 2003-12-23 2003-12-23 Metodo e circuito di individuazione di celle di memoria anomale.

Country Status (2)

Country Link
US (1) US7072239B2 (it)
IT (1) ITVA20030052A1 (it)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3028932B2 (ja) * 1996-09-27 2000-04-04 日本電気株式会社 入出力バッファメモリ回路

Also Published As

Publication number Publication date
US7072239B2 (en) 2006-07-04
US20050169089A1 (en) 2005-08-04

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