FR2728391B1 - - Google Patents

Info

Publication number
FR2728391B1
FR2728391B1 FR9415540A FR9415540A FR2728391B1 FR 2728391 B1 FR2728391 B1 FR 2728391B1 FR 9415540 A FR9415540 A FR 9415540A FR 9415540 A FR9415540 A FR 9415540A FR 2728391 B1 FR2728391 B1 FR 2728391B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9415540A
Other languages
French (fr)
Other versions
FR2728391A1 (fr
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US08/357,021 priority Critical patent/US5444014A/en
Application filed filed Critical
Priority to FR9415540A priority patent/FR2728391A1/fr
Priority to DE4445344A priority patent/DE4445344C2/de
Priority to GB9425589A priority patent/GB2296374B/en
Publication of FR2728391A1 publication Critical patent/FR2728391A1/fr
Application granted granted Critical
Publication of FR2728391B1 publication Critical patent/FR2728391B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H10D10/054—Forming extrinsic base regions on silicon substrate after insulating device isolation in vertical BJTs having single crystalline emitter, collector or base regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/041—Manufacture or treatment of thin-film BJTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/018—Manufacture or treatment of isolation regions comprising dielectric materials using selective deposition of crystalline silicon, e.g. using epitaxial growth of silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges
FR9415540A 1994-12-16 1994-12-19 Procede de fabrication d'un substrat soi et d'un transistor bipolaire l'utilisant Granted FR2728391A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US08/357,021 US5444014A (en) 1994-12-16 1994-12-16 Method for fabricating semiconductor device
FR9415540A FR2728391A1 (fr) 1994-12-16 1994-12-19 Procede de fabrication d'un substrat soi et d'un transistor bipolaire l'utilisant
DE4445344A DE4445344C2 (de) 1994-12-16 1994-12-19 Verfahren zur Herstellung einer Halbleitervorrichtung
GB9425589A GB2296374B (en) 1994-12-16 1994-12-19 Fabricating semiconductor devices

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US08/357,021 US5444014A (en) 1994-12-16 1994-12-16 Method for fabricating semiconductor device
FR9415540A FR2728391A1 (fr) 1994-12-16 1994-12-19 Procede de fabrication d'un substrat soi et d'un transistor bipolaire l'utilisant
DE4445344A DE4445344C2 (de) 1994-12-16 1994-12-19 Verfahren zur Herstellung einer Halbleitervorrichtung
GB9425589A GB2296374B (en) 1994-12-16 1994-12-19 Fabricating semiconductor devices

Publications (2)

Publication Number Publication Date
FR2728391A1 FR2728391A1 (fr) 1996-06-21
FR2728391B1 true FR2728391B1 (enExample) 1997-02-07

Family

ID=39561846

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9415540A Granted FR2728391A1 (fr) 1994-12-16 1994-12-19 Procede de fabrication d'un substrat soi et d'un transistor bipolaire l'utilisant

Country Status (4)

Country Link
US (1) US5444014A (enExample)
DE (1) DE4445344C2 (enExample)
FR (1) FR2728391A1 (enExample)
GB (1) GB2296374B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2917919B2 (ja) * 1996-06-20 1999-07-12 日本電気株式会社 半導体基板およびその製造方法、並びに半導体素子
JP3075204B2 (ja) * 1997-02-28 2000-08-14 日本電気株式会社 半導体装置の製造方法
FR2812451B1 (fr) * 2000-07-28 2003-01-10 St Microelectronics Sa Procede de fabrication d'un ensemble silicium sur isolant a ilots minces semi-conducteurs entoures d'un materiau isolant
US6552374B2 (en) * 2001-01-17 2003-04-22 Asb, Inc. Method of manufacturing bipolar device and structure thereof
DE10124038A1 (de) * 2001-05-16 2002-11-21 Atmel Germany Gmbh Verfahren zur Herstellung vergrabener Bereiche
DE10124032B4 (de) * 2001-05-16 2011-02-17 Telefunken Semiconductors Gmbh & Co. Kg Verfahren zur Herstellung von Bauelementen auf einem SOI-Wafer
US7262087B2 (en) * 2004-12-14 2007-08-28 International Business Machines Corporation Dual stressed SOI substrates
US7635599B2 (en) * 2005-09-29 2009-12-22 Hitachi Global Storage Technologies Netherlands B.V. Three terminal magnetic sensing devices having base lead layers in-plane with collector substrate materials and methods of making the same
CN116403902B (zh) * 2023-06-08 2023-08-18 微龛(广州)半导体有限公司 一种垂直双极性结型晶体管及其制作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3929528A (en) * 1973-01-12 1975-12-30 Motorola Inc Fabrication of monocriptalline silicon on insulating substrates utilizing selective etching and deposition techniques
US3909332A (en) * 1973-06-04 1975-09-30 Gen Electric Bonding process for dielectric isolation of single crystal semiconductor structures
JPS5779634A (en) * 1980-11-06 1982-05-18 Fujitsu Ltd Manufacture of semiconductor device
EP0146613B1 (en) * 1983-06-13 1990-12-05 Ncr Corporation Process for fabricating semiconductor structures
JPS60113435A (ja) * 1983-11-25 1985-06-19 Hitachi Ltd 半導体装置およびその製造方法
JPS6412543A (en) * 1987-07-07 1989-01-17 Toshiba Corp Manufacture of semiconductor device
US5057443A (en) * 1988-06-29 1991-10-15 Texas Instruments Incorporated Method for fabricating a trench bipolar transistor
JPH02214120A (ja) * 1989-02-15 1990-08-27 Fujitsu Ltd 半導体装置の製造方法
EP0418421B1 (de) * 1989-09-22 1998-08-12 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Bipolartransistors mit verminderter Basis/Kollektor-Kapazität
US5266517A (en) * 1991-12-17 1993-11-30 Texas Instruments Incorporated Method for forming a sealed interface on a semiconductor device
JPH05251292A (ja) * 1992-03-06 1993-09-28 Nec Corp 半導体装置の製造方法
US5234535A (en) * 1992-12-10 1993-08-10 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
US5318663A (en) * 1992-12-23 1994-06-07 International Business Machines Corporation Method for thinning SOI films having improved thickness uniformity

Also Published As

Publication number Publication date
DE4445344A1 (de) 1996-06-27
US5444014A (en) 1995-08-22
GB2296374B (en) 1999-03-24
GB9425589D0 (en) 1995-02-15
GB2296374A (en) 1996-06-26
FR2728391A1 (fr) 1996-06-21
DE4445344C2 (de) 1996-10-02

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Legal Events

Date Code Title Description
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Effective date: 20060831