FR2812451B1 - Procede de fabrication d'un ensemble silicium sur isolant a ilots minces semi-conducteurs entoures d'un materiau isolant - Google Patents

Procede de fabrication d'un ensemble silicium sur isolant a ilots minces semi-conducteurs entoures d'un materiau isolant

Info

Publication number
FR2812451B1
FR2812451B1 FR0009987A FR0009987A FR2812451B1 FR 2812451 B1 FR2812451 B1 FR 2812451B1 FR 0009987 A FR0009987 A FR 0009987A FR 0009987 A FR0009987 A FR 0009987A FR 2812451 B1 FR2812451 B1 FR 2812451B1
Authority
FR
France
Prior art keywords
semiconductors
surrounded
silicon
manufacturing
insulating material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0009987A
Other languages
English (en)
Other versions
FR2812451A1 (fr
Inventor
Herve Jaouen
Goascoz Vincent Le
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0009987A priority Critical patent/FR2812451B1/fr
Priority to US09/915,753 priority patent/US6593204B2/en
Publication of FR2812451A1 publication Critical patent/FR2812451A1/fr
Application granted granted Critical
Publication of FR2812451B1 publication Critical patent/FR2812451B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76278—Vertical isolation by selective deposition of single crystal silicon, i.e. SEG techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
FR0009987A 2000-07-28 2000-07-28 Procede de fabrication d'un ensemble silicium sur isolant a ilots minces semi-conducteurs entoures d'un materiau isolant Expired - Fee Related FR2812451B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0009987A FR2812451B1 (fr) 2000-07-28 2000-07-28 Procede de fabrication d'un ensemble silicium sur isolant a ilots minces semi-conducteurs entoures d'un materiau isolant
US09/915,753 US6593204B2 (en) 2000-07-28 2001-07-26 Method of fabricating a silicon-on-insulator system with thin semiconductor islets surrounded by an insulative material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0009987A FR2812451B1 (fr) 2000-07-28 2000-07-28 Procede de fabrication d'un ensemble silicium sur isolant a ilots minces semi-conducteurs entoures d'un materiau isolant

Publications (2)

Publication Number Publication Date
FR2812451A1 FR2812451A1 (fr) 2002-02-01
FR2812451B1 true FR2812451B1 (fr) 2003-01-10

Family

ID=8853071

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0009987A Expired - Fee Related FR2812451B1 (fr) 2000-07-28 2000-07-28 Procede de fabrication d'un ensemble silicium sur isolant a ilots minces semi-conducteurs entoures d'un materiau isolant

Country Status (2)

Country Link
US (1) US6593204B2 (fr)
FR (1) FR2812451B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7042052B2 (en) * 2003-02-10 2006-05-09 Micron Technology, Inc. Transistor constructions and electronic devices

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081061A (en) * 1990-02-23 1992-01-14 Harris Corporation Manufacturing ultra-thin dielectrically isolated wafers
US5073230A (en) * 1990-04-17 1991-12-17 Arizona Board Of Regents Acting On Behalf Of Arizona State University Means and methods of lifting and relocating an epitaxial device layer
JP2643015B2 (ja) * 1990-08-13 1997-08-20 シャープ株式会社 完全誘電体分離基板の製造方法
DE4033508C1 (en) * 1990-10-21 1992-03-12 Hoefflinger, Prof. Dr., 7000 Stuttgart, De Silicon@ wafer mfr. for high yield - by oxidising silicon@ disc, etching filling with silicon@, bonding with thick layer oxide layer and thinning for sepd. silicon areas
DE69332407T2 (de) * 1992-06-17 2003-06-18 Harris Corp Herstellung von Halbleiteranordnungen auf SOI substraten
US5260233A (en) * 1992-11-06 1993-11-09 International Business Machines Corporation Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding
US5585661A (en) * 1993-08-18 1996-12-17 Harris Corporation Sub-micron bonded SOI by trench planarization
US5444014A (en) * 1994-12-16 1995-08-22 Electronics And Telecommunications Research Institute Method for fabricating semiconductor device
JP2692659B2 (ja) * 1995-10-13 1997-12-17 日本電気株式会社 Ｓｏｉ基板および該ｓｏｉ基板の製造方法
US6140205A (en) * 1997-04-23 2000-10-31 Elantec, Inc. Method of forming retrograde well in bonded waffers
JP4144047B2 (ja) * 1997-08-20 2008-09-03 株式会社デンソー 半導体基板の製造方法
US6372599B1 (en) * 1999-01-14 2002-04-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
FR2812451A1 (fr) 2002-02-01
US20020019083A1 (en) 2002-02-14
US6593204B2 (en) 2003-07-15

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Effective date: 20080331