FR2724511B1 - Systeme de telecommunications en multiplex du type maitre-esclave et boucle a phase asservie s'appliquant a ce systeme - Google Patents

Systeme de telecommunications en multiplex du type maitre-esclave et boucle a phase asservie s'appliquant a ce systeme

Info

Publication number
FR2724511B1
FR2724511B1 FR9510522A FR9510522A FR2724511B1 FR 2724511 B1 FR2724511 B1 FR 2724511B1 FR 9510522 A FR9510522 A FR 9510522A FR 9510522 A FR9510522 A FR 9510522A FR 2724511 B1 FR2724511 B1 FR 2724511B1
Authority
FR
France
Prior art keywords
slave
master
moving phase
phase loop
type multiplex
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9510522A
Other languages
English (en)
Other versions
FR2724511A1 (fr
Inventor
Yoshio Inagaki
Masayuki Takami
Masahiro Kataoka
Taro Shibagaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP6216157A external-priority patent/JPH0884074A/ja
Priority claimed from JP26971094A external-priority patent/JP3277080B2/ja
Priority claimed from JP7014642A external-priority patent/JPH08204548A/ja
Priority claimed from JP7014555A external-priority patent/JPH08204552A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of FR2724511A1 publication Critical patent/FR2724511A1/fr
Application granted granted Critical
Publication of FR2724511B1 publication Critical patent/FR2724511B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
FR9510522A 1994-09-09 1995-09-08 Systeme de telecommunications en multiplex du type maitre-esclave et boucle a phase asservie s'appliquant a ce systeme Expired - Fee Related FR2724511B1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP6216157A JPH0884074A (ja) 1994-09-09 1994-09-09 Ｐｌｌ回路
JP26971094A JP3277080B2 (ja) 1994-11-02 1994-11-02 マスター・スレーブ多重通信システム
JP1373995 1995-01-31
JP7014642A JPH08204548A (ja) 1995-01-31 1995-01-31 ディジタルｐｌｌ回路およびそのディジタルフィルタ
JP7014555A JPH08204552A (ja) 1995-01-31 1995-01-31 ディジタルｐｌｌ回路およびそのディジタルフィルタ

Publications (2)

Publication Number Publication Date
FR2724511A1 FR2724511A1 (fr) 1996-03-15
FR2724511B1 true FR2724511B1 (fr) 2000-11-17

Family

ID=27519550

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9510522A Expired - Fee Related FR2724511B1 (fr) 1994-09-09 1995-09-08 Systeme de telecommunications en multiplex du type maitre-esclave et boucle a phase asservie s'appliquant a ce systeme

Country Status (3)

Country Link
US (1) US5648964A (fr)
FR (1) FR2724511B1 (fr)
GB (1) GB2293062B (fr)

Families Citing this family (38)

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US5539357A (en) * 1995-09-15 1996-07-23 Thomson Consumer Electronics, Inc. Phase locked loop
JP3350349B2 (ja) * 1995-09-26 2002-11-25 株式会社日立製作所 ディジタル情報信号再生回路及びディジタル情報装置
SE517602C2 (sv) * 1995-10-20 2002-06-25 Ericsson Telefon Ab L M Fastlåst loop
JP2919335B2 (ja) * 1996-02-06 1999-07-12 埼玉日本電気株式会社 Ａｆｃ型発振回路
US5710720A (en) * 1996-04-30 1998-01-20 Board Of Regents Of The University Of Nebraska Phase lock loop based system and method for decomposing and tracking decomposed frequency components of a signal, with application to vibration compensation system
US5903616A (en) * 1996-10-08 1999-05-11 Advanced Micro Devices, Inc. Synchronous clock multiplexer
CA2217840C (fr) * 1997-10-09 2005-05-03 Northern Telecom Limited Systeme de synchronization a multiples modes d'operations
US6108389A (en) * 1997-12-11 2000-08-22 Motorola, Inc. Synchronization of internal coder-decoders of multiple microprocessors
US5974058A (en) * 1998-03-16 1999-10-26 Storage Technology Corporation System and method for multiplexing serial links
US6931087B1 (en) * 1998-04-17 2005-08-16 Invensys Systems, Inc. Feedforward clock switching circuit
EP0954104A1 (fr) * 1998-04-28 1999-11-03 Siemens Aktiengesellschaft Boucle à verrouillage de phase comprenant un comparateur de phase analogique et un filtre numérique
JP2000068824A (ja) 1998-08-21 2000-03-03 Fujitsu Ltd Ｐｌｌ制御装置、ｐｌｌ制御方法およびリミッタ
US6928106B1 (en) * 1998-08-28 2005-08-09 Broadcom Corporation Phy control module for a multi-pair gigabit transceiver
US6363129B1 (en) * 1998-11-09 2002-03-26 Broadcom Corporation Timing recovery system for a multi-pair gigabit transceiver
US6807228B2 (en) 1998-11-13 2004-10-19 Broadcom Corporation Dynamic regulation of power consumption of a high-speed communication system
JP2000174616A (ja) * 1998-12-04 2000-06-23 Fujitsu Ltd 半導体集積回路
US6359945B1 (en) 1999-01-25 2002-03-19 Sun Microsystems, Inc. Phase locked loop and method that provide fail-over redundant clocking
DE60035679T2 (de) * 1999-04-22 2008-06-05 Broadcom Corp., Irvine Gigabit-ethernt mit zeitverschiebungen zwischen verdrillten leitungspaaren
US6194969B1 (en) 1999-05-19 2001-02-27 Sun Microsystems, Inc. System and method for providing master and slave phase-aligned clocks
SE517967C2 (sv) 2000-03-23 2002-08-06 Ericsson Telefon Ab L M System och förfarande för klocksignalgenerering
US6839391B2 (en) * 2002-01-08 2005-01-04 Motorola, Inc. Method and apparatus for a redundant clock
US7051235B2 (en) * 2002-08-27 2006-05-23 Sun Microsystems, Inc. Clock distribution architecture having clock and power failure protection
CN100428630C (zh) * 2003-08-29 2008-10-22 华为技术有限公司 同步数字体系系统时钟及产生方法
US7415002B2 (en) * 2003-10-24 2008-08-19 Brocade Communications, Inc. Circuit synchronization over asynchronous links
US7171318B2 (en) * 2004-06-17 2007-01-30 International Business Machines Corporation PLL filter leakage sensor
US7173495B1 (en) 2005-04-05 2007-02-06 Pericom Semiconductor Corp Redundant back-up PLL oscillator phase-locked to primary oscillator with fail-over to back-up oscillator without a third oscillator
US7697647B1 (en) * 2005-10-03 2010-04-13 Avaya Inc. Method and system for switching between two (or more) reference signals for clock synchronization
US8532243B2 (en) * 2007-02-12 2013-09-10 Silicon Laboratories Inc. Digital hold in a phase-locked loop
US7885365B2 (en) * 2007-08-31 2011-02-08 International Business Machines Corporation Low-power, low-area high-speed receiver architecture
US8339165B2 (en) * 2009-12-07 2012-12-25 Qualcomm Incorporated Configurable digital-analog phase locked loop
US8446191B2 (en) 2009-12-07 2013-05-21 Qualcomm Incorporated Phase locked loop with digital compensation for analog integration
US8406258B1 (en) * 2010-04-01 2013-03-26 Altera Corporation Apparatus and methods for low-jitter transceiver clocking
JP6371096B2 (ja) * 2014-04-09 2018-08-08 ザインエレクトロニクス株式会社 受信装置
US10514720B1 (en) 2018-06-19 2019-12-24 Aura Semiconductor Pvt. Ltd Hitless switching when generating an output clock derived from multiple redundant input clocks
CN109474925B (zh) * 2018-12-28 2022-04-22 Tcl移动通信科技（宁波）有限公司 基于sim模块的时钟设置方法、移动终端及存储介质
US11588489B1 (en) 2021-10-06 2023-02-21 Shaoxing Yuanfang Semiconductor Co., Ltd. Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lock
US11923864B2 (en) 2021-10-18 2024-03-05 Shaoxing Yuanfang Semiconductor Co., Ltd. Fast switching of output frequency of a phase locked loop (PLL)
US11967965B2 (en) 2021-11-03 2024-04-23 Shaoxing Yuanfang Semiconductor Co., Ltd. Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4349914A (en) * 1980-04-01 1982-09-14 Ford Aerospace & Communications Corp. Bit synchronous switching system for space diversity operation
US4511859A (en) * 1982-08-30 1985-04-16 At&T Bell Laboratories Apparatus for generating a common output signal as a function of any of a plurality of diverse input signals
US4633193A (en) * 1985-12-02 1986-12-30 At&T Bell Laboratories Clock circuit synchronizer using a frequency synthesizer controlled by a frequency estimator
US4651103A (en) * 1985-12-30 1987-03-17 At&T Company Phase adjustment system
US4860285A (en) * 1987-10-21 1989-08-22 Advanced Micro Devices, Inc. Master/slave synchronizer
US4849993A (en) * 1987-12-10 1989-07-18 Silicon General, Inc. Clock holdover circuit
JP2568110B2 (ja) * 1988-07-15 1996-12-25 パイオニア株式会社 フェーズロックドループ回路
JPH0744537B2 (ja) * 1990-01-19 1995-05-15 オタリ株式会社 ディジタル信号時間差補正回路
JP3120994B2 (ja) * 1990-05-11 2000-12-25 キヤノン株式会社 デジタル交換装置
US5059925A (en) * 1990-09-28 1991-10-22 Stratacom, Inc. Method and apparatus for transparently switching clock sources
US5515403A (en) * 1994-06-21 1996-05-07 Dsc Communications Corporation Apparatus and method for clock alignment and switching

Also Published As

Publication number Publication date
GB2293062B (en) 1996-12-04
GB9518007D0 (en) 1995-11-08
FR2724511A1 (fr) 1996-03-15
GB2293062A (en) 1996-03-13
US5648964A (en) 1997-07-15

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Effective date: 20130531