FR2709899A1 - Method of detecting a loss of synchronisation in a digital communications network, and terminal for implementing the method - Google Patents

Abstract

Method of detecting a loss of logic synchronisation between a sending terminal linked by a digital data channel (19) to a receiver terminal, in which - the sender sends a defined sequence of sending code words (25) into a synchronisation channel (29), - the receiver reads a sequence of reception code words (66) identical to the sending sequence (25) and compares the sending and receiving code words, - in the event of lack of identity in sending (25) and receiving (66) code words, the receiver generates a loss of logic synchronisation signal (8) in order to resynchronise the two terminals. Application to transmission of coded speech.

Description

Method for detecting loss of synchronization in a network

digital communication

  and terminal for implementing the method.

  The present invention relates to a method for detecting a loss of logical synchronization between a data sending terminal and a receiving digital communication network terminal. It will be noted that the invention does not relate to the analog detection of the phase of the received data bits, which would be used to control an oscillator fixing the instants for reading the bits.

received at the receiver input.

  On a data transmission link, there may be disturbances causing errors in the reception of data. If these data are digital, they can be protected by a password.

  code providing redundancy for this data.

  However, an error detecting and correcting code can only correct errors in the receiver insofar as they are limited in number. Otherwise, the

  receiver invalidates an entire data block.

  However, when it is a question of transmitting data by separate cells, of a group of bytes, as in transmission according to the technique of Multiplexing by Asychronous Transfer (ATM), a transmitted cell can be

  lost without it being immediately detected.

  If the flow of data transmitted by successive cells has previously passed through a scrambling circuit, a scrambling circuit receiving the data leaving the receiver will then be logically desynchronized with respect to the scrambling circuit because it will be 2--2 behind one cell, c ' that is, it will try, unsuccessfully, to unscramble the bits of the cell following that which has been lost, by means of a

  electronic key provided for the lost cell.

  This loss of logical synchronization thus prevents the unblocking, therefore the operation, of the cells following that which has been lost, until an algorithm for detecting such a fault begins a procedure to resynchronize the descrambler, by determining then canceling the above delay. In the meantime, many cells remain unusable and, if it is a transmission of data which must be exploited immediately, like digitized speech, the unscrambled data are definitively lost, which can generate a perceptible silence of duration ,

unacceptable.

  The present invention aims to overcome this drawback.

  To this end, it relates first of all to a method for detecting a loss of logical synchronization between two terminals, one transmitting and supplying a data channel, the other, receiving, of a digital communication network, characterized by the fact that it comprises the following steps: - a synchronization channel is reserved in the data channel in which the transmitter transmits a determined sequence of emission code words, - the receiver reads, at the rate of arrival of the emission code words, a sequence of reception code words identical to the emission sequence and compares the emission and reception code words, - 3- - in the event of identity error of transmit and receive code words, the receiver generates a loss of logical synchronization signal to resynchronize the

two terminals.

  We thus immediately detect, at the physical level of the transmission, the loss of logical synchronization, whereas, if this same detection were to be performed by interpretation of the flow of the transmitted data, it

  would be late and often uncertain.

  Advantageously, when comparing two transmission and reception code words, their respective positions in the two sequences are determined and these positions are compared to provide a resynchronization signal representative of an offset between

said positions.

  Resynchronization can thus be immediate.

  Advantageously also, on transmission, the bits of the data channel and the bits of the data channel are combined.

  synchronization in successive bytes.

  As the usual logical components transmit the bits by bytes, one can use a single chain of

transmission for both channels.

  The invention is of particular interest in the case where, on transmission, the data is scrambled, and o, on reception, the data is unscrambled under the possible control of the loss of logic synchronization signal and of the resynchronization signal . The invention also relates to a terminal of a digital communication network, characterized in that it is arranged for the implementation of the method of the invention and that it comprises sequencing means for inserting, into a data transmission channel, a synchronization channel for transmitting a

  specified sequence of emission code words.

  In the case of bidirectional links, the above terminal advantageously comprises other sequencing means, for extracting from another data channel another synchronization channel and receiving another determined sequence of emission code words, as well as comparator means arranged to receive emission code words and reception code words and generate a signal of loss of logical synchronization in the event of a lack of identity of the code words

transmission and reception.

  The invention will be better understood using the

  following description of preferred embodiment

  of the transmitter and the receiver applying the method according to the invention, with reference to the appended drawing, in which: - Figure 1 is a block diagram of a link connecting a transmitter to a receiver implementing the method of the invention, - Figure 2 represents, as a function of time t, data cells transmitted according to the ATM technique, - Figure 3 is a block diagram of a logic synchronization transmitter circuit according to the invention, -5 - - Figure 4 is a block diagram of a receiver circuit detecting a loss of logical synchronization according to the invention and - Figure 5 illustrates, as a function of time t, the way

  according to which the transmitted bits are grouped.

  The method of the invention is, in this example, implemented in a digital speech transmission link, scrambled and transmitted over a digital network using the principle of transmission by

  Multiplexing by Asynchronous Transfer (ATM).

  The bits of the data to be transmitted come from a transmitting terminal and pass there through a scrambling circuit 1, represented in FIG. 1, controlling, through a logic synchronization circuit 2, a transmitter 3 connected to a line 4 of the digital network of

communication 84.

  A receiver terminal includes a receiver 5, connected as an input to line 4, the output of which attacks a detector 6 of loss of logical synchronization between the transmitter 3

and the receiver 5.

  The detector 6 supplies, to a descrambler circuit 7, the data bits received as well as a signal 8 of loss of logical synchronization, if such is the case, accompanied here by a resynchronization signal 9 indicating the

  magnitude of the corresponding logic offset.

  In a known manner, the transmitter 3 receives a continuous stream of bits and, in this example, transmits them in packets, or cells 10 represented in FIG. 2, constituted, very schematically, of a data field 11 and a field 12 of service and address signals. The cells 10 arrive at random times at the receiver 5 which, by a buffer memory, restores a

continuous data flow.

  It will be understood that the temporary division into cells 10 of the data stream, for their transport on the physical link 4, is carried out in a systematic manner which does not take into account the meaning of these data, linked to the application. , or exploitation,

planned.

  In other words, if, as explained below, the data are arranged in a series of patterns for their exploitation, these successive patterns will, in order to be accommodated in the successive cells, be cut out a priori from a pattern to the next, depending on the relative lengths of a pattern and the field

11 of cells 10.

  In the present application, the scrambler 1 receives bits of digitized speech from an encoder not shown and, in known manner, transcodes the bit stream into a scrambled bit stream, by means of an electronic key controlling a circuit transcoding can take a large number of cyclically reproducing states and constituting a transcoding pattern, of known length, here much greater than that

a cell 10.

  The bits of the pattern 20 are here transmitted at a fixed rate in blocks of seven bits, in a data channel 19 (FIG. 3), to a buffer register 21 with parallel / parallel access, at the input of the circuit 2. The seven outputs corresponding to register 21 are connected to a multiplexer 22 with eight inputs addressed by three bits 23 - 7 - of low weight of a counter 26 controlled by a circuit

27.

  Three following bits 24, of intermediate weight, of counter 26 address a multiplexer 28 with eight inputs receiving the following eight bits 25, of high weight, of counter 26, which constitute a code word of emission, or number of synchronization of program. A synchronization channel 29 arises at the output of the multiplexer 28 and arrives at the eighth input of the multiplexer 22. The output of the multiplexer 22 provides

the transmitter 3 the bits to be transmitted.

  At the output of the receiver 5, the detector 6 temporarily stores each byte received in a buffer register 61 with parallel / parallel access, shown in FIG. 4. Seven outputs, corresponding to the memory positions of the register 61 which contain the seven scrambled data bits, are connected to the inputs of a multiplexer

  2 62 connected at output to the descrambler 7.

  A shift register 63, with eight parallel outputs, receives the synchronization channel 29, that is to say the eighth bit of the register 61, and advances at the rate of a clock signal 64, coming from a counter. of a time base 65 slaved to the rhythm of the bits coming from the receiver 5. The signal 64 also controls the storage in the buffer register 61. FIG. 5 illustrates, as a function of time t, the way in which the bits of the data channel 19 and signaling channel 29 are grouped and

  appear at the output of register 61.

  The multiplexer 62 is addressed by the time base 65 at a rate seven times faster than that of the signal 64, in order to ensure the speed adaptation, between the receiver 5 and the descrambler 7, required by

  extracting the bit from synchronization channel 29.

  A counter 66 advances, under the control of the time base 65, at the rate of a signal 67, eight times less than that of the clock signal 64. The counter 66 is initialized, at the start of data transmission, by l sending of a START signal, 70, consisting, here, of two of the synchronization words, possibly more, but which do not differ by one, which allows a circuit 69 to detect the reception of the START signal, 70 ,

and initialize the counter 66.

  The counter 66 has eight outputs providing a reception code word, here a reception synchronization number, which are connected to the subtractor 68, which is also connected to the eight outputs of the register 63. The subtractor 68 provides the signal 8, in the form of a bit indicating, in the activated state, that the result of the subtraction between the number of transmission code (25) and the number of reception code is different from zero. It provides the descrambler 7, in addition, the result

  itself in the form of a resynchronization signal 9.

  The outputs of the subtractor 68 supplying the signals 8 and 9 are validated by the clock signal 67, which has a form factor of 1/8 in order to limit this validation to the only period of the signal 64 for which the eight bits 25 d '' the same number of transmission synchronizations are, in the absence of fault

  transmission, stored in register 63.

  The operation of the above circuits will now

be explained.

  -9- The scrambled data from the scrambler 1 is transmitted to the transmitter 3 by the multiplexer 22 of the circuit 2, which ensures the timing adaptation required by the fact that it inserts, in each byte transmitted, a bit synchronization (25) from the counter 26, each time the three least significant bits 23 carry out an addressing cycle of the multiplexer 22, ie eight steps ahead of the counter 26. At the start of each such cycle, the three bits 24 address another input of the multiplexer 28, so that the eight most significant bits 25 are read after eight cycles, ie 64 steps ahead of the counter 26. The number represented by the eight most significant bits 25, which is the code word or synchronization number intended for the receiver 5, is then incremented by one unit and is transmitted, as explained above, during the following 64 steps. The counter 26 returns to the same state after transmission of the

  256 possible combinations of most significant bits 25.

  The transmitter 3 and the receiver 5 ensure, in a known manner, the transmission of the data stream by means of the

cells 10.

  The register 61 of the detector 6 receiving the bytes, the bit (25) of the synchronization channel 29 is each time stored in the register 63. After reception of the eight bits 25 belonging to the same transmitted number, the outputs of the subtractor 68 are validated by signal 67 during a period of signal 64, so that comparator 68 reads, at the rate of arrival of the emission code words, the sequence, which follows a predetermined progression here in unitary steps, of code words reception. This sequence, consisting of the successive numbers appearing at the output of the counter 66, is identical to the transmission sequence and the comparator 68

  compare the transmit and receive code words.

  -10- In the event of an identity fault between the number of the transmission code word represented by the eight bits 25 and that of the expected reception code word, supplied by the counter 66, the loss of synchronization signal 8 passes in the active state and the signal 9 provides the value of the delay of the reception counter 66 relative to the most significant 25 of the transmission counter 26. A unit in this difference therefore corresponds to a block of 64 steps of the counter 26, c is the length of eight bytes necessary to transmit a number of a code word

transmission (25).

  We thus detect and correct a delay of up to

255 blocks of eight bytes.

  It will be noted that it is possible to detect and measure a delay less than a block of eight bytes by providing a register 63 extended to two bytes and by comparing the homologous bits 25 in each of the two bytes, by means of eight exclusive OR gates ( not shown) serving as a comparator. The least significant bit of each byte of bits 25 occupies in register 63, however taking into account the progressive shift due to the advance of register 63, the position for which the corresponding exclusive OR permanently provides a logic level 1 in exit, indicating a permanent discrepancy. Indeed, this least significant bit changes state from one code word to the next, while any other of the other seven bits 25 remains unchanged at least once after a change

number status.

  The detection of the position of the least significant of the bits 25 can thus be carried out in a little more than one period of the clock signal 64. Knowing the offset of this position relative to the normal position, one -11- can then supply the eight corresponding inputs of the subtractor 68 through eight multiplexers with eight inputs, not shown, respectively. These multiplexers are addressed by three bits representing this offset, in order to apply to subtractor 68 a byte of bits 25 correctly framed, that is to say corresponding to the same synchronization number, byte may have an offset between 0 and 7 bits relative to its intended position (register 63 such as

  shown, only one byte).

  The value of the corresponding offset can then be supplied with the resynchronization signal 9, for

  increase the accuracy of the information it provides.

  The signals 8 and 9 also serve to resynchronize the detector 6, to restore good physical reception of the data. In addition, in this application, the signal 8 is used to control the descrambler 7 so that it begins a resynchronization procedure. Such a procedure is known and is therefore not described here. In this example, the resynchronization signal 9 allows the descrambler 7 to resynchronize in a deterministic manner, therefore rapid, since it suffices, to recover its correct position in the scrambling / descrambling pattern, to correct its position

  erroneous by the value of its delay, or offset.

  In the case where, as here, the major risk is the loss of a cell 10, the data field 11 of the cells has a size, in number of bytes, which is an integer multiple of the number of bytes, here eight bytes, necessary to transmit the eight bits 25 of the synchronization channel 29. Thus, the offset, in the event of a fault, is equal to this integer multiple, which facilitates

correction of the fault.

  -12- It could also have been provided, contrary to what was indicated initially, to transmit the pattern 20 in a determined whole number of cells 10, being able for example to transmit eight bytes each in the field 11. That is to say -to say that it is advantageous to transmit the data in packets of a determined number of cells 10 by synchronizing the patterns 20 and the cells 10, for example by choosing a pattern length 20 which is an integer multiple of the length of the field 11, so that the loss of a cell 10 affects only one motif 20, in a predetermined position among several. In order to increase the bit rate offered to the data of the scrambler 1, provision could have been made to insert the bit of the transmission synchronization word only in a limited number of transmitted bytes, for example every eight bytes, in order to transmit 63 bits of speech,

  against 56 previously, in each block of eight bytes.

  Provision could also have been made to reserve at least one bit location for synchronization channel 29 only in determined bytes separated from one another by a determined number of bytes. In particular, provision could have been made to transmit several bits of the synchronization channel 29 in some of the bytes transmitted, possibly eight bits, even, as above, reserving the other bytes for the data of the scrambler 1. In others terms, the synchronization channel 29 can be multiplexed spatially and / or temporally with the data channel

  19, in a fixed or variable manner known to the detector 6.

  In the case where transmissions in one direction and the other should be able to be established between the two terminals, each would advantageously include the

  transmission means 1-3 and reception means 5-7.

  It will be understood that the format of the data field 11 described, here eight sets of one byte of bits, is given only by way of example and that sets of bits of size other than the byte can be chosen and grouped in any number desired to constitute the

data field of a cell.

-14-

Claims (13)

  1. Method for detecting a loss of logical synchronization between two terminals, one transmitting and supplying a data channel (19), the other, receiving, of a digital communication network, characterized in that it comprises the following steps: - a synchronization channel (29) is reserved in the data channel (19) in which the transmitter transmits a determined sequence of emission code words (25), - the receiver reads , at the rate of arrival of the transmission code words (25), a sequence of reception code words (66) identical to the transmission sequence (25) and compares the transmission and reception code words , - in the event of a fault in the identity of emission code (25) and reception code (66) words, the receiver generates a loss of logic synchronization signal (8) for resynchronize the two terminals.   2. Method according to claim 1, in which the successive code words are numbers (25) whose   values follow a predetermined progression.   3. Method according to one of claims 1 and 2, in   which, when comparing two transmit (25) and receive (66) code words, their respective positions in the two sequences are determined and these positions are compared to provide a resynchronization signal (9) representative of a mismatch between said positions.   4. Method according to one of claims 1 to 3, in   which, on transmission, combines the bits of the data channel (19) and the bits of the synchronization channel (29) in successive bytes.   5. Method according to claim 4, in which the synchronization channel (29) is reserved at least one bit location only in determined bytes separated from each other by a determined number of bytes.   6. Method according to one of claims 1 to 5, in   which data (19, 29) is transmitted in packets of a   determined number of cells (10) of eight bytes.   7. Method according to one of claims 3 to 6, in   which, on transmission, scrambles the data and, on reception, scrambles the data under the possible control of the loss of logic synchronization signal   (8) and the resynchronization signal (9).   8. Terminal of a digital communication network, characterized in that it is arranged for the implementation of the method of claim 1 and that it includes sequencing means (22, 26-28) for inserting, into a data transmission channel (19), a synchronization channel (29) for transmitting a   specified sequence of emission code words.   9. Terminal according to claim 8, in which the sequencing means comprise memory means (26,28) for supplying bits representative of the transmission code words (25) and a multiplexer (22) arranged to alternately receive bits of the data channel   (19) and bits of the memory means (26). -16-   10. Terminal according to one of claims 8 and 9, in   which is provided with an output scrambling circuit (1).   11. Terminal according to one of claims 8 to 10, in   which other sequencing means (63, 65, 69) are provided, for extracting, from another data channel (19), another synchronization channel (29) and receiving another determined sequence of code words d transmission (25), as well as comparator means (68) arranged to receive emission code words (25) and reception code words (66) and generate a loss of logic synchronization signal (8) in failure to identify the emission code words (25) and reception (66).   12. Device according to claim 11 in which, the successive code words (25; 66) being numbers arranged according to a progression with fixed pitch, the comparator means comprise a subtractor (68) arranged to supply a signal (9) representative of the difference   between the compared code words (25, 66).   13. Device according to one of claims 11 and 12,   in which an output descrambler circuit (7) is provided.