FR2597687A1 - Method and device for rapid regeneration of the integrity of the binary flowrate in a plesiochronous network - Google Patents

Abstract

In a plesiochronous transmission network 1, 2, 3, a tag generator 7 is arranged in the transmitter 1, and a tag processing circuit 14 in the receiver 2, these tags being bits multiplexed in each time interval of the frames transmitted in the network. The tag generator includes essentially a pseudo-random generator.

Description

METHOD AND DEVICE FOR FAST REGENERATION OF
INTEGRITY OF BIT RATE IN A NETWORK
PLESIOCHRONOUS
The present invention relates to a method for rapidly regenerating the integrity of the bit rate in a plesiochronous network, as well as to a device for implementing this method.

 The present invention is an improvement made to the process and to the device for regenerating the integrity of the bit rate in a plesiochronous network which were the subject of French patent application 86.00322 filed on January 10, 1986.

 As in the invention cited in reference, the method applies to transmission by frames. These frames are composed of a succession of time intervals, the format and usage of which are fixed by a standard and which each contain the data relating to a particular link according to the well-known method of time multiplexing. The invention applies to framed connections according to the CEPT standard as well as to other standards, for example the RITA standard. In the latter two cases, the time interval "0" is devoted to the transmission of the frame alignment character and another time interval to the signaling exchanges between switching centers. A network is said to be plesiochronous when the switching centers are driven at different but very similar frequencies. A switching center which receives a frame sent at a frequency slightly higher than its own cannot take into account all the information it receives and will have to periodically catch up by losing data. A switching center that receives a frame transmitted at a frequency slightly lower than its own will find itself periodically in need of data and will be forced to supplement with non-significant data. In either case, the number of bits leaving the switching center which corresponds to each time interval of the incoming frame is disturbed and does not respect the integrity of the bit rate. This phenomenon which has no effect on communications "clear" telephone calls cause the total loss of intelligibility on digital data communications and on all encrypted links due to the sliding of the encrypted message with respect to the decryption key.

 As in the invention cited in reference, the regeneration of the integrity of the bit rate is done independently for each time interval by devoting a fraction of the capacity of the channel to integrate a "marker" which evolves according to a predetermined sequence. The loss of integrity results in an anomaly in the sequence. In the invention cited in reference, the marker sequence contains a lock code which will be recognized without ambiguity and the correction of the flow integrity is based on the fact that the number of bits transmitted between two lock codes is known The correction can only be made when the lock code is recognized and the message transmitted by the channel becomes unintelligible during the time interval, or latency, which elapses until the arrival and recognition of the lock code. next lock.

 In the process which is the subject of the present invention, the drawback cited above is overcome with the aid of marker sequences in which the locking code is distributed throughout the sequence. For this, use is made of the properties of pseudo-random sequences such as those produced by way of nonlimiting example by looped shift register generators.

The present invention will be better understood on reading the description of an embodiment taken as a nonlimiting example illustrated by the appended drawing in which:
- Figure 1 is a block diagram of a network according to the invention;
- Figure 2 shows a fragment of the frame transmitted between network switching centers;
- Figure 3 is the block diagram of a marker generator associated with the origin transmitter center;
- Figure B is the block diagram of the binary integrity regenerator device associated with the receiving receiving center;
FIG. 5 is an alternative embodiment of the circuit of FIG. 4, and
FIG. 6 is the diagram of an advantageous variant of part of the circuit of FIG. 5.

 The present invention is implemented in plesiochronous communication networks in which the digital information (speech, various data) is transmitted on a time support, called frame, consisting of time intervals, the number of binary elements contained in a time interval, and the number of time intervals per frame varying according to the standards.

 According to the CEPT standard, a frame consists of thirty-two time intervals of eight binary elements each. According to the RITA standard, the frame consists of twenty-four time intervals of six binary elements each.

 The possible bit rate in each time interval is 64 k bits / s for a CEPT frame, and 48 k bits / s for a RITA frame.

 In a homogeneous digital network, the order of the binary elements is invariant. We can therefore make them play independent roles, and therefore multiplex several sub-channels in the same time interval.

 By way of nonlimiting example, to ensure the interconnection of a CEPT network with a RITA network, an interface called "gateway" is used. In the CEPT to RITA direction, only six binary elements per time interval of the CEPT frame can be transmitted by this interface, the other two being lost.

In the RITA to CEPT direction, six of the eight bits of a time slot in the CEPT frame are significant, the two additional bits being either non-significant or redundant.

 Furthermore, certain systems make it possible to coagulate (combine) several consecutive time intervals to form a single channel having an information rate multiple of the basic rate.

 The circuits for processing the marker on the transmitter side of a plesiochronous communication network will only be described very briefly below, since these circuits are commonplace in themselves, and can be easily adapted by those skilled in the art. art to the variants that it can be brought to adopt according to the characteristics of this network.

 The circuits schematically represented in FIG. 1 comprise an origin transmitter 1 connected to a destination receiver 2 by transit circuits 3, the set of elements 1 to 3 forming part or all of a plesiochronous network.

 Transit circuits 3 can include several intermediate receivers RI1 to Rîn cooperating with several intermediate transmitters El1 to El n via links LI to Ln by cables, radio-relay systems, etc .; similar links 4, 5 connecting elements I and 2 to element 3.

 The original transmitter 1 essentially comprises an information generator 6 and a marker generator 7 connected to a multiplexer 8, the output of which is connected by a transmission circuit 9 to the link 4. The generator 6 digitizes, if necessary where appropriate, the useful signals which it receives from various analog sources and constitute frames, a fragment of which is shown in FIG. 2.

Each time interval, for example ITi, comprises, in a preferred embodiment of the invention, two positions of binary elements reserved for the markers M1 and M2 introduced at the level of the multiplexer 8 by the generator 7 and B positions for the signals useful. The marker generator 7 and the multiplexer 8 are, of course, synchronized, by means not shown and obvious to those skilled in the art, with the frames of the generator 6. The transmission circuit 9 is a circuit capable of send on the link 4 the frames coming from the multiplexer 8: it is for example a telephone transmission circuit for a link 4 by telephone cable.

The destination receiver 2 includes a reception circuit 10 capable of receiving the signals arriving via the link 5. It is followed by a demultiplexer 11 capable of presenting useful information signals on one output 12, and on two outputs 13.1 and 13.2 the markers introduced by the generator 7. This demultiplexer 11 is, of course, synchronized with the received frames. If the positions of the markers are fixed, the demultiplexer sends it to the outputs
13.1 and 13.2 the binary elements of all the time intervals found at these positions. If these positions change, the demultiplexer 11 is also controlled as a function of the law of evolution, which is obviously the same in the transmitter I and in the receiver 2.

This law of evolution can, for example, be determined by a pseudo-random sequence generator, its counterpart being placed in the receiver 2. The sequence used can also have cryptological qualities, that is to say that it cannot be reproduced without having knowledge of an encryption key and that this key cannot be calculated from a sample of the sequence. The outputs 12 and 131, 132 of the demultiplexer 11 are connected to a marker processing circuit 14 which will be described below with reference to FIG. 2. This circuit 14 is connected to an information processing circuit 15, corresponding to the generator 6 of the transmitter 1. This circuit 15 processes the useful binary information elements of the time intervals received to restore this information, if necessary after digital-analog conversion.

FIG. 3 represents a particular embodiment of the marker generator 16 based on an 8-stage shift register looped back by the addition operator modulo 2 referenced 17 to produce the pseudo-random sequence of maximum length of 28 ~ I bits = 255 bits. This type of generator is well known to those skilled in the art. The locations of the intermediate taps are determined from the coefficients of primitive polynomials whose degree is equal to the total number of stages. In the example in FIG. 3, it is the polynomial X8 + x6 + X5 + X3 + 1. A complete list of these polynomes can be found in works such as that of
WW PETERSON, 3.E. WELDON "Error correcting codes", Ed.2
Appendix C. This type of generator is provided by way of nonlimiting example. We can also make such generators based on a non-linear loopback operator, which allows them to be given cryptological qualities.

 The marker signal M2 which leaves in 18.2 is obtained in the example chosen by taking the complement of M1 available in 18.1 using the inverter 19, but it is understood that the two markers M1 and M2 can be produced independently of each other, and may have cycles of equal or different length, these cycles having different content.

 If one examines the sequence of the marker M1 (or M2) in a window of 8 consecutive bits one notes that: - the generator can emit a permanent continuation of O: this case must be eliminated using appropriate auxiliary circuits evident for the 'skilled in the art and not shown in Figure 3 - the generator provides a series of bytes where the same values reappear periodically. In the case considered in the example, the period is 255 bytes. All the values (except the code 00000000 which must never appear) follow one another in a well defined order. Take the origin of the cyle of marking the instant of appearance of an easily recognized byte, for example 11111111.

There is a one-to-one correspondence between each byte value and its time of appearance in the cycle, and therefore the total number of bits transmitted and which should have arrived at the recipient receiver since the start of the cycle.

A first particular example of embodiment of the circuits 14 and 15 of FIG. 1 is shown in more detail in FIG. 4. The marking code M1 is presented at the serial input 13.1 of the shift register RAD referenced 23. After a period d establishment which corresponds to the loading in RAD of the first 8 successive bits, the bytes available on the parallel output 22 will be presented in the order defined by the logic of the pseudo-random sequence generator of the original transmitter. The B data bits present simultaneously at 12 are stored in the buffer memory TR at the address defined by the byte present on output 22. If, following a loss of integrity, a break occurs in the sequence of the marker M 1, the code contained in RAD will take erroneous values for 8 frames and the 8 characters of data received during this period will register at wrong addresses with possible "overwriting" of data not yet used. Then the sequential succession will resume its normal course. The data are read in the buffer memory TR in the same sequential order as in writing: the reading addresses are supplied by a pseudo-random sequence generator GSPA referenced 26 whose logic is the same as that of the transmitter The sequence of operations (reading and saving in the buffer memory
TR, read-write multiplexing via the multiplexer 24 connected to the outputs of 23 and 26, and shift of the registers 23 and of the register that comprises 26) is under the control of a clock 27 synchronized on the receiving end. At the start of communications, the circuit is initialized by forcing the GSPA generator into the state corresponding to the offset of half a period with the code present at output 22.

In the case of the generator in FIG. 3, it is possible for example to wait for the passage of the code 11111111 to force the register of the generator 26 thanks to its parallel input EP to 11010111, ie an offset of 127 steps. It is obvious that the number of address bits chosen, therefore the length of the shift registers of the generators, the generator polynomial, the size of the buffer memory have been given by way of nonlimiting illustration of the scope of the invention.

A loss of integrity or a transmission error affecting one or more bits of the MI marker causes an error in the addressing of writing data in the 8 frames following
TR. On reading there will be 16 erroneous characters distributed randomly in a block of 255 characters. The circuit of Figure 5 is a variant of that of Figure 4 to partially overcome this defect. The circuit in Figure 5 has two marker inputs 13.1 and 13.2 for M1 and M2 respectively. We consider here that M1 and M2 are complementary to each other. These two inputs are connected to an exclusive OU 34 whose output 33 is connected to an input of an AND gate 35. The output 36 of the gate 35 is connected to the serial input of an eight-cell shift register 37. The parallel output (on eight bits) of register 37 is connected to an input of an AND gate 38 whose output C is connected to the written command input reading of a buffer memory 125 which receives data from input 12 of the successive time intervals of the signals received by the destination receiver.

 The input 13.1 is also connected to the serial input of a shift register 123, certain parallel outputs of which are connected to an adder 31, thus forming with this latter a pseudo-random generator 29. The input 13.1 is finally connected via a logic inverter 30 to the modulo 2 adder referenced 31. The output 32 of the modulo 2 adder referenced 31 is connected to the second input of gate 35.

 The parallel output A of the register 123 is connected on the one hand to an input of a multiplexer 124 and on the other hand via a logic initialization circuit 128 (consisting for example of a code comparator which detects the passage of the register 123 in the state "11111111" at the parallel input of the register 129 of another pseudo-random generator 126.

 The parallel output of the generator 126 register is connected to the second input of the multiplexer 124.

 A clock signal generator 127 is connected to the other input B of the gate 38, to the control input of the multiplexer 124, and to the clock signal inputs of the registers 37, 123 and 129.

The circuit of FIG. 5, inhibits the write function during the 8 frames which follow the following anomalies: - Marking bits M1 and M2 not coherent with each other: for example
M1 and M2 must be complementary to each other. If this condition is not satisfied, the output 33 of the exclusive OR gate 34 is at 0.

- Bit M 1 entering out of sequence. Logical condition 29 includes a modulo 2 adder whose input variables are connected on the same sockets as in the pseudo-random sequence generators of the transmitter and GSPA referenced 126 of the receiver to which the complement of the bit MI obtained is added. using the inverter 30. If M1 is out of sequence (or false), output 32 is at 0.

 The 8-bit shift register RINH 37 is normally completely filled with "1". If any of the fault conditions described above appear, a 0 is loaded into the register and puts 8 frames to be eliminated. During all this time the door ET 38 prohibits the passage of the buffer TR 125 in writing. There is therefore backup of the data recorded previously. The data which has not been recorded gives a reading of TR a packet of 8 consecutive incorrect characters.

The circuit of FIG. 6 is a variant of the circuit 130 of FIG. 5, comprising the elements 34, 35, 37, 38, 29, 30. The door 38 of the circuit of FIG. 5 being eliminated in this variant,
The clock 127 is directly connected (connection wire between B and C) to the read / write command input of the memory 125.

The two inputs 13.1 and 13.2 receiving M1 and M2 are each connected to the serial input of a pseudo-random sequence controller 61, 62 respectively, identical to the circuit 29 in FIG. 4, the input M1 directly, and the input M2 via a logic inverter 63 (the circuit of FIG. 6 relates to the case where M2 is the logical complement of M1). Each of the wires of the parallel output of the register
RADI of generator 61 is connected to a first input of a door
AND of a set 64 of eight doors AND with two inputs each. The output of the generator adder 61 is connected to the serial input of an eight-stage register 69, the eight parallel outputs of which are connected to the eight inputs of an AND gate 66. The output of gate 66 is connected to all the second entrances to the doors of set 64.

 Each of the wires of the parallel output of the register RAD2 of the generator 62 is connected to a first input of an AND gate of a set 67 of eight AND gates with two inputs each. The output of the generator adder 62 is connected to the serial input of an eight-stage register 68 whose eight parallel outputs are connected to the eight inputs of an AND gate 69. The output of gate 69 is connected to all the second entrances to the doors of set 67.

 The outputs of the eight doors of the assembly 64 are each connected to a first input of a door OR of a set 70 of eight doors, the outputs of the eight doors of the assembly 67 are each connected to a second input of these same doors OR.

 In this variant, when the sequence of the marker M1 is correctly received, there must be in the register 65 only "I", which also gives a "1" at the exit of the gate 66, this "1" allowing the configuration present in the register RAD1 of the generator 61 to pass the gates 64, and therefore to arrive at the output A.

Similarly, if the marking M2, complementary to M1, and inverted by the inverter 63, is correctly received, a "1" at the exit of door 69 authorizes the passage of the configuration contained in the register
RAD2 of generator 62 via gates 67 and 70 towards output A. Of course, If the two sequences of M1 and M2 are good, we find in A only one configuration since, by hypothesis M2 is the complement of Ml and that the content of RAD2 is equal to that of RADI. If only one of them is good, it goes to A, and if none is good, there are eight "0" in A which correspond to the address "0" of the buffer memory, address not normally used.

Claims (11)

 1. Method for regenerating binary integrity in a plesiochronous network, for transmission by frames of several time intervals, according to which one multiplexes on transmission, in synchronism with the information whose number one wishes to regenerate on reception binary elements transmitted, the binary elements of useful information with at least one binary element called "marking", characterized by the fact that on transmission there are produced marking cycles of which no group of n consecutive bits of a cycle has the same value as any other group of the same length of the same cycle, and upon reception, each group of markers is examined to determine whether the information received is incorrect and / or incomplete.  2. Method according to claim 1, characterized in that the marker cycles are produced by at least one pseudo-random generator.  3. Method according to one of claims 1 or 2, characterized in that on reception, on arrival of each marking bit, this bit as well as the (nl) preceding bits, which are read, are memorized the different sequences thus memorized, in the order in which they have been memorized, with an offset at least equal to that which can be produced during the duration of a communication, and that the multiplexed information data are validated with the sequences of corresponding markers if these sequences read correspond to those having been issued.  4. Method according to one of the preceding claims, characterized in that the markers are multiplexed on fixed positions of each time interval.  5. Method according to one of claims 1 to 3, characterized in that the markers are multiplexed on positions, evolving according to determinable parameters, of each time interval.  6. Method according to one of the preceding claims, characterized in that the marker consists of two bits (M1, M2) equal.  7. Method according to one of claims 1 to 5, characterized in that one of the markers is the binary complement of the other.  8. Device for regenerating binary integrity in a plesiochronous network, for transmission by frames of several time intervals, characterized in that it comprises, in the transmitter (1), a generator (7) of markers to shift register (16) with N stages looped back by a linear combinational logic circuit (17) generating the maximum sequence of length 2N-1, and by the fact that it comprises in the receiver (2) a demultiplexer (11) separating the information data of the marker bits with which they are multiplexed, the output of markers (13.1,  13.2) of this demultiplexer being connected to a device (14) comprising a buffer memory (125) for the information data addressed successively in writing by a device (130) for memorizing sequences of incident markers, and in reading by a generator (126) similar to the marker generator of the transmitter.  9. Device according to claim 8, characterized in that the device for memorizing sequences of markers (130) comprises a shift register (23 or 123) with N cells, the code present in this register constituting the storage address in the buffer memory (2S or 125) of the information bits received with the last marker loaded in the shift register.  10. Device according to one of claims 8 or 9, characterized in that an auxiliary circuit (34, 35, 37) is used to inhibit the writing in the buffer memory (12S) during the N time intervals which follow the detection of an incorrect marker.  He. Device according to one of claims 8 to 10, characterized in that it comprises an initialization logic (28, 128) connected to the generator (26, 126) of the receiver, this logic acting only once, after the establishment of a communication, at the moment when the code present in the device for memorizing sequences of markers passes through a predetermined value (V).  12. Device according to claim 11, characterized in that the value (V) loaded into the generator (26) of the receiver is that reached P cycles after having passed through said predetermined value (V), P being the most integer neighbor of 2N / 2