GB2293731A

GB2293731A - Detecting loss of synchronisation in a digital communication system

Info

Publication number: GB2293731A
Application number: GB9419837A
Authority: GB
Inventors: Denis Dumont
Original assignee: Sagem SA
Current assignee: Sagem SA
Priority date: 1993-09-07
Filing date: 1994-10-01
Publication date: 1996-04-03
Anticipated expiration: 2014-10-01
Also published as: NL9401602A; FR2709899B1; NL194630C; GB2293731B; NL194630B; DE4435215A1; CH689850A5; FR2709899A1; GB9419837D0; DE4435215B4

Description

1 2293731 The present invention relates to a method for the detection of a

loss of logical synchronisation between a data transmitter terminal and a receiver terminal of a digital communication system. It will be noted that the invention does not relate to the analog detection of the phase of the data bits received, which would serve to control an oscillator fixing the instants for reading bits received at the input of the receiver.

On a data transmission connection, disturbances may occur producing errors in the reception of the data. If these data are digital, they may be protected by a code word ensuring redundancy for these data. However, a detector code and error-correction code is able, in the receiver, to correct the errors solely to the extent that they are of a limited number. Otherwise, the receiver invalidates an entire block of data.

Now, when it is a question of a transmission of data by separate cells, of a group of octets, as in the transmission according to the technique of Asynchronous Transfer Multiplexing (ATM), one transmitted cell may be lost without this being detected immediately.

If the flow of data transmitted by successive cells has previously passed through a scrambler circuit, a descrambler circuit receiving the data leaving the receiver will then be desynchronised logically with respect to the scrambler circuit, since it will be behind by one cell, that is to say that it will attempt, without success, to descramble the bits of the cell following that which has been lost, electronic key provided for the lost cell.

This loss of logical synchronisation by means of an thus prevents the descrambling, thus the exploitation, of the cells following that which has been lost, until an algorithm for the detection of such a fault initiates a procedure for resynchronising the descrambler, thus determining then cancelling the above delay. In the meantime, numerous cells cannot be exploited and, if it is a question of a transmission of data which must be exploited immediately, such as the digitized word, the unscrambled data are definitively lost, which may produce a silence 10 of perceptible duration, which is unacceptable.

The present drawback.

invention intends to obviate this To this end, it relates first of all to a method for the detection of a loss of logical synchronisation between two terminals, one a transmitter and supplying a data channel, the other a receiver, of a digital communication system, characterised by the fact that it comprises the following stages:

- there is reserved, in the data channel, a synchronisa- tion channel in which the transmitter transmits a predetermined sequence of transmission code words, - the receiver reads, at the arrival rate of the transmission code words, a sequence of reception code words identical to the transmission sequence and compares the transmission code words and reception code words, - if the transmission code words and reception code words are not identical, the receiver produces a loss of logical synchronisation signal in order to resynchronise the two terminals.

one thus detects the loss of logical synchronisation immediately, at the physical level of the transmission, 3 whereas, if this same detection were to be carried out by interpretation of the flow of data transmitted, it would occur with a delay and would often be uncertain.

Advantageously, at the time of the comparison of the two transmission and reception code words, their respective positions in the two sequences are determined and these positions are compared in order to provide a resynchronisation signal representative of a shift between said positions.

The resynchronisation may thus be immediate.

Also advantageously, upon transmission, the bits from the data channel and the bits from the synchronisation channel are combined in successive octets.

Since the customary logical components transmit the bits by octets, one can use a single transmission chain for the two channels.

The invention has a quite particular advantage in the case where, upon transmission, the data are scrambled, and where, upon reception, the data are unscrambled under the possible control of the loss of logical synchronisation signal and of the resynchronisation signal.

The invention digital communication also relates to a terminal of a characterised by the out the method system, fact that it is arranged for carrying of the invention and that it comprises sequencer means for inserting, in a data transmission channel, a synchronisation channel for transmitting a predetermined sequence of transmission code words.

- 4 Inthe case of bidirectional connections, the above terminal advantageously comprises other sequencer means, for extracting, from another data channel, another synchronisation channel and receiving another predeter mined sequence of transmission code words, as well as comparator means arranged to receive transmission code words and a loss of logical mission and reception code words are not identical.

reception code words synchronisation signal and to produce if the transThe invention will be better understood by means of the ensuing description of the preferred embodiment of the transmitter and receiver using the method according to the invention, with reference to the accompanying drawings, in which:

Figure 1 is a block diagram of a connection connecting a transmitter to a receiver using the method of the invention, Figure 2 shows, as a function of the time t, data cells transmitted according to the ATM technique, Figure 3 is a block diagram of a logical synchronisation transmitter circuit according to the invention, Figure 4 is a block diagram of a receiver circuit for detecting loss of logical synchronisation according to the invention and Figure 5 illustrates, as a function of the time t, the manner in which the transmitted bits are regrouped.

The method of the invention is, in this example, used in a connection for the transmission of a digitized word, which is scrambled and transmitted on a digital system using the principle of transmission by Asynchronous Transfer Multiplexing (ATM).

The data bits to be transmitted originate from a transmitter terminal and pass therein through a scrambler circuit 1, illustrated in Figure 1, controlling, by way of a logic synchronisation circuit 2, a transmitter 3 connected to a line 4 of the digital communication system 84.

A receiver terminal comprises a receiver 5, connected at the input to the line 4, the output of which drives a logical synchronisation loss detector 6 between the transmitter 3 and the receiver 5.

The detector 6 supplies, to a descrambler circuit 7, the bits of data received as well as a logical synchronisation loss signal 8, if this is the case, in this case accompanied by a resynchronisation signal 9 indicating the magnitude of the corresponding logical shift.

In known manner, the transmitter 3 receives a continuous flow of bits and, in this example, transmits them in batches, or cells 10 illustrated in Figure 2, constituted, very diagrammatically, by an area 11 of data and by an area 12 of service and address signals. The cells 10 reach the receiver 5 at random instants, which receiver, by means of a buffer memory, restores a continuous flow of data.

It will be clearly understood that the temporary cutting-up, into cells 10 of the flow of data, for their transmission on the physical connection 4, is carried out systematically, which does not take into account the significance of these data, linked with the application, or exploitation, provided.

In other words, if, as explained hereafter, the data are arranged in a succession of patterns for their exploitation, these successive patterns will be, in order to be housed in the successive cells 10, cut up in a manner which is a priori variable from one pattern to the next, depending on the relative lengths of one pattern and on the area of data 11 of the cells 10.

In the present application, the scrambler 1 receives bits of digitized word coming and, in known manner, transcodes from a coder (not shown) the flow of bits into 10 a scrambled flow of bits, by means of an electronic key controlling a transcoding circuit able to adopt a large number of states which are reproduced cyclically and constitute a transcoding pattern 20, of known length, in this case clearly greater than that of a cell 10.

constitute The bits of the pattern 20 are in this case transmitted at a fixed rate in blocks of seven bits, in a data channel 19 (Figure 3) to a buffer register 21 having parallel/parallel access, at the input of the circuit 2. The seven corresponding outputs of the register 21 are connected to a multiplexer 22 having eight inputs addressed by three bits 23 of low weight of a counter 26 controlled by a clock circuit 27.

Three following bits 24, of intermediate weight, from the counter 26 address a multiplexer 28 having eight inputs receiving the eight following bits 25, of considerable weight, from the counter 26, which a transmission code word, synchronisation number. A synchronisation channel 29 originates at the output of the multiplexer 28 and arrives at the eighth input of the multiplexer 22. The output of the multiplexer 22 supplies the transmitter 3 with the bits to be transmitted.

or transmission 7 At the output of the receiver 5, the detector 6 temporarily stores each octet received in a buffer register 61 having parallel/parallel access, illustrated in Figure 4. Seven outputs, corresponding to the memory positions of the register 61 which contain the seven bits of scrambled data, are connected to the inputs of a multiplexer 62 connected at the output to the descrambler 7.

A shift register 63, having eight parallel outputs, receives the synchronisation channel 29, i.e. the eighth bit from the register 61 and advances at the rate of a clock signal 64, originating from a time base counter 65 controlled by the rate of the bits coming from the receiver 5. The signal 64 also controls the memorisation in the buffer register 61. Figure 5 illustrates, as a function of the time t, the manner in which the bits of the data channel 19 and of the signalling channel 29 are grouped and appear at the output of the register 61.

The multiplexer 62 is addressed by the time base at a rate seven times faster than that of the signal 64, in order to ensure the adaptation of speed, between the receiver 5 and the descrambler 7, necessitated by the extraction of the bit from the synchronisation channel 29.

A counter 66 advances, under the control of the time base 65, at the rate of a signal 67, eight times less than that of the clock signal 64. The counter 66 is initialised, at the beginning of data transmission, by the sending of a START signal 70, constituted in this case by but which do a circuit 69 two synchronisation words, possibly more, not differ by one unit, which enables to detect the receiving of the START signal - 8 and to initialise the counter 66.

The counter 66 comprises eight outputs supplying a reception code word, in this case a reception synchronisation number, which are connected to the subtractor 68, connected furthermore to the eight outputs of the register 63. The subtractor 68 supplies the signal 8, in the form of one bit indicating, in the activated state, that the result of the subtraction between the transmission code number 25 and the reception code number is different to zero. By way of addition, it supplies the descrambler 7 with the result itself in the form of a resynchronisation signal 9.

The outputs of the subtractor 68 supplying the signals 8 and 9 are validated by the clock signal 67, which has a factor of form of 1/8 in order to limit this validation to the only period of the signal 64 for which the eight bits 25 of the same transmission synchronisation number are, in the absence of a transmission fault, stored in the register 63.

The operation of explained.

the above circuits will now be The scrambled data coming from the scrambler 1 are transmitted to the transmitter 3 by the multiplexer 22 of the circuit 2, which ensures the adaptation of the rate necessitated by the fact that it inserts, in each octet transmitted, a synchronisation bit 25 coming from the counter 26, each time the three bits of low weight 23 carry out a cycle of addressing the multiplexer 22, or eight advance steps of the counter 26. At the beginning of each such cycle, the three bits 24 address another input of the multiplexer 28, so that the eight bits 25 of considerable weight are - 9 read at the end of eight cycles, namely 64 advance steps of the counter 26. The number represented by the eight bits of considerable weight 25, which is the code word or synchronisation number intended for the receiver 5, is then incremented by one unit and is transmitted, as explained above, at the time of the following 64 steps. The counter 26 again passes through the same state after transmission of the 256 possible combinations of the bits of considerable weight 25.

The transmitter 3 and the receiver 5 ensure, in known manner, the transmission of the flow of data by means of cells 10.

Since the register 61 of the detector 6 receives the octets, the bit 25 of the synchronisation channel 29 is on each occasion memorised in the register 63. After receiving eight bits 25 belonging to the same transmitted number, the outputs of the subtractor 68 are validated by the signal 67 for a period of the signal 64, so that the comparator 68 reads, at the arrival rate of the transmission code words, the sequence, which follows a predetermined progression in this case with a unitary step, of the reception code words. This sequence, constituted by the successive numbers appearing at the output of the counter 66, is identical to the transmission sequence and the comparator 68 compares the transmission and reception code words.

In the case of a lack of identity number of the transmission code word represented by the eight bits 25 and that of the reception code word provided, supplied by the counter 66, the loss of synchronisation signal 8 passes to the active state and the signal 9 supplies the value of the delay of the reception counter 66 with respect to the considerable between the - weights 25 of the transmission counter 26. One unit in this difference thus corresponds to a block of 64 steps of the counter 26, that is to say to the length of eight octets necessary for transmitting a number 5 of a transmission code word 25.

A delay which may reach 255 blocks of eight octets is thus detected and corrected.

It will be noted that it is possible to detect and measure a delay less than one block of eight octets by providing a register 63 extended to two octets and by comparing the similar bits 25 octets, by means of eight exclusive OR gates (not shown) serving as a comparator. The bit of lowest weight of each octet of bits 25 occupies in the register 63, however taking into account the progressive shift due to the advance of the register 63, the position for which the corresponding exclusive OR gate permanently supplies a logic level 1 at the output, indicating permanent disagreement. In fact, this bit of the lowest weight changes state from one code word number to the next, whereas any other of the seven other bits 25 remains unchanged at least once after a change of state of the number.

in each of the two The detection of the position of the lowest weight 25 of the bits 25 may thus take place in a little more than one period of the clock signal 64. Knowing the shift of this position with respect to the normal position, one can then supply the eight corresponding inputs of the subtractor 68 by way of respectively eight multi- plexers with eight inputs, which are not shown. These multiplexers are addressed by three bits representing this shift, in order to apply to the subtractor 68 an octet of bits 25, which agrees correctlYP i.e. corresponding to the same synchronisation number, the octet being able to comprise a shiftcEbetween 0 with respect to its provided position as shown, comprising only one octet).

The value of the corresponding shift may be supplied with the resynchronisation signal order to increase the accuracy of the information it supplies.

and 7 bits (register 63 The signals 8 and 9 also serve to resynchronise the detector 6, in order to re-establish the good physical reception of the data. In addition, in this application, the signal 8 serves to control the descrambler 7 in order that it initiates a resynchronisation procedure.

Such a procedure is known and is therefore not described here. In this example, the resynchronisation signal 9 enables the descrambler 7 to resynchronise in a deter minest manner, therefore quickly, since it is sufficient, in order to relocate its correct position in the scram bling/descrambling pattern, to correct its erroneous position by the value of its delay, or shift.

In the case where, as here, the major risk is the loss of a cell 10, the area of data 11 of the cells has a size, in the number of octets, which is a whole multiple of the number of octets, in this case eight octets, necessary for transmitting the eight bits 25 of the synchronisation channel 29. Thus, the shift, in the case of a fault, is equal to this whole multiple, which facilitates the correction of the fault.

Contrary to what has been stated initially, it would also have been possible to transmit the pattern 20 in a predetermined whole number of cells 10, it being possible for example to transmit eight octets each in the area 11. That is to say that it is advantageous to transmit the data in batches of a predetermined 12 number of cells 10 by synchronising the patterns 20 and the cells 10, for example by choosing a length of the pattern 20 which is a whole multiple of the length of the area 11, in order that the loss of one cell 10 affects only a single pattern 20, in a position predetermined amongst several.

In order to increase the rate of flow offered to the data of the scrambler 1, it would have been possible to insert the bit of the transmission synchronisation word solely in a limited number of octets transmitted, for example every eight octets, in order to transmit 63 word bits, as against 56 previously, in each block of eight octets. It would also have been possible to reserve for the synchronisation channel 29 at least one bit location solely in predetermined octets separated from each other by a predetermined number of octets. In particular, one could have transmitted several bits from the synchronisation channel 29 in certain of the transmitted octets, possibly eight bits, even if, as above, the other octets were reserved for the data of the scrambler 1. In other words, the synchronisation channel 29 may be multiplexed in a spatial and/or temporal manner with the data channel 19, in a known fixed or variable manner of the detector 6.

In the case where transmissions in one direction and the other should be able to be established between the two terminals, each would advantageously comprise the transmission means 1-3 and the reception means 5-7.

It will be understood that the format of the data area 11 described, in this case eight sets of one octet of bits, is given solely by way of example and that 13 - sets of bits of a size other than the octet may be chosen and combined in any desired number in order to constitute the data area of a cell.

Claims

1. Method for the detection of a loss of logical synchronisation between two terminals, one a transmitter and supplying a data channel (19), the other a receiver, of a digital communication system, characterised by the fact that it comprises the following stages:

- there is reserved, in the data channel (19), a synchronisation channel (29) in which the transmitter transmits a predetermined sequence of transmission code words (25), - the receiver reads, at the arrival rate of the transmission code words (25), a sequence of reception code words (66) identical to the transmission sequence (25) and compares the transmission and reception code words, - in the case of a lack of identity between the transmission code words (25) and reception code words (66), the receiver produces a loss of logical synchronisation signal (8) in order to resynchronise the two terminals.

2. Method according to Claim 1, in which the successive code words are numbers (25) whereof the values follow a predetermined progression.

3. Method according to one of Claims 1 and 2, in which, at the time of comparison of two transmission and reception code words (25) and (66) respectively, their respective positions in the two sequences are determined and these positions are compared in order to supply a resynchronisation signal (9) representative of a shift between said positions.

4. Method according to one of Claims 1 to 3, in which, upon transmission, the bits from the data channel (19) - and the bits from the synchronisation channel (29) are combined in successive octets.

5. Method according to Claim 4, in which one reserves for the synchronisation channel (29) at least one bit location solely in predetermined octets separated from each other by a predetermined number of octets.

6. Method according to one of Claims 1 to 5, in which the data (19, 29) are transmitted in batches of a predetermined number of cells (10) of eight octets.

7. Method according to one of Claims 3 to 6,in whictk upon transmission, the data are scrambled and, on reception, the data are unscrambled under the possible control of the loss of logical synchronisation signal (8) and of the resynchronisation signal (9).

8. Terminal of a digital communication system, characterised by the fact that it is arranged for carrying out the method of Claim 1 and that it comprises sequencer means (22, 26-28) for inserting, in a data transmission channel (19), a synchronisation channel (29) in order to transmit a predetermined sequence of transmission code words.

9. Terminal according to Claim 8, in which, the sequencer means comprise memory means (26, 28) for supplying bits representative of the transmission code words (25) and a multiplexer (22) arranged to receive, alternately, bits from the data channel (19) and bits from the memory means (26).

10. Terminal according to one of Claims 8 and 9, in which an output scrambler circuit (1) is provided.

16 -

11. Terminal according to one of Claims 8 to 10, in which other sequencer means (63, 65, 69) are provided, in order to extract, from another data channel (19), another synchronisation channel (29) and to receive another predetermined sequence of transmission words (25), as well as comparator means (68) arranged for receiving transmission code words (25) and reception code words (66) and for producing a loss of logical synchronisation signal (8) in the case of a lack of identity between the transmission code words (25) and reception code words (66).

12. Device according to Claim 11 in which, since the successive code words (25; 66) are numbers stored according to a fixed step progression, the comparator means comprise a subtractor (68) arranged in order to supply a signal (9) representative of the difference between the code words compared (25, 66).

13. Device according to one of Claims 11 and 12, in which an output descrambler circuit (7) is provided.