FR2844652A1 - High level data link control protocol plesiochrone stream transmission having digital word stream input channels aligning time base/frequency then multiplexing/processing - Google Patents

Abstract

The plesiochrone stream transmission process to a central unit has frames following the HDLC protocol. The digital words (F1 to Fn) are processed (4) in the central unit. There are a number of input circuits (1-1 to 1-n) with the input streams and a time multiplexer (2) connected in series. The multiplexer output (3) links to the central processing unit. The input circuits align the input stream on the same time base and same frequency.

Description

The present invention relates to a system for transmitting a

  plurality of plesiochronous flows towards a central processing unit, such as the flows transported by frames according to a oriented protocol, such as the so-called HDLC (Highlevel Data Link Control) protocol. According to an application of the present invention, such flows 5 originate from the communication channels, called DCCs (Data Communication Channel) present in a synchronous frame,

such as an SDH or SONET frame.

  It will be recalled below that a bit-oriented protocol such as the HDLC protocol is a protocol implemented in layer 2 of the ISO model (link layer of this model) and that it provides for the transport of data in frames of which FIG . 1 gives a representation. As can be seen in this Fig. 1, an HDLC frame is delimited by flags (flag in English terminology) and includes several fields which are respectively: an address field used to identify a particular terminal, a command field for transmission control, a length data field arbitrary in which are inserted the data to be transmitted and a control field (Checksum). The flags correspond to the sequence 011 111 10 (7E in hexadecimal) which must not be found in any of the fields filled in the frame. At rest, this sequence is transmitted continuously. In addition, on the transmitter side, a mechanism for inserting a bit at 0 after the appearance of five consecutive 1 to 20 bits makes it possible to avoid the appearance of the flag sequence 7E in the filled fields. On the receiver side, this bit at 0 is removed. An escape character is sometimes

also used.

  It is also recalled that in parallel to the transport of the data on synchronous links SDH (Synchonous Data Hierarchy) or SONET, communication channels are provided which are used essentially for the management of communications on the synchronous links. More particularly, the data streams are transported on the synchronous links in frames, called in the SDH system STM-n frames, which include a section header SOH (Section OverHead) in which are filled with management fields of the section. concerned. In this SOH section header, there are three bytes Dl, D2 and D3 which together form a channel of

  communication at 192 kbits / s, channel called DCC.

  As mentioned above, these communication channels are mainly used for transporting communication management data over synchronous links. This management data is processed in a central processing unit common to all the STM-n ports that comprises SDH or SONET synchronous link multiplexing equipment. They are therefore transmitted to this central unit and to do this, in particular because their flow is not permanent, they are put in

  forms according to a bit-oriented protocol such as the HDLC protocol.

  However, when a multiplex equipment has a number

  important for ports, the routing of data flows from these communication channels to the central processing unit poses the problem of the number of links required and the number of ports that said central processing unit must include. This results in a complexity of the system which the object of the present invention is to reduce.

  To this problem, is added the fact that the flows of the communication channels are plesiochronous flows and that thus, they can be offset in the

  time or even have slightly different clock periods.

  The object of the present invention is therefore to provide a system 15 for transmitting a plurality of plesiochronous flows to a central processing unit which is of reduced complexity with regard in particular to the number of links required and the number of ports that must include said central processing unit and which solves the problems linked to the fact that these plesiochronous flows can be offset in the

  time and / or have slightly different clock periods.

  To do this, the invention therefore relates to a system for transmitting a plurality of plesiochronous flows to a central processing unit, such as the flows transported by frames according to a bit-oriented protocol, such as the so-called HDLC protocol, the data of the flows being processed in said central processing unit. This system is characterized in that it consists of a plurality of input circuits, the inputs of which are provided to be able to receive plesiochronous data streams and of a time multiplexer, each of the inputs of which is connected to an output of an input circuit and the output of which is on a link to said central processing unit, the input circuits being provided for aligning the plesiochronous data flows with a

  same time base and on the same frequency.

  According to an additional characteristic, the frames of said bit-oriented protocol being accompanied by a clock signal, said transmission system is characterized in that it comprises a FIFO type memory provided for, on the one hand, entering the bytes from the incoming stream at the rate of the clock signal accompanying said incoming stream and, on the other hand, outputting said bytes in order to deliver them on the output of said

  device at the rate of the clock signal delivered by an internal clock.

  According to another additional characteristic, the frames of said oriented protocol being delimited by flags consisting of a determined bit sequence, said transmission system is characterized in that each of said input circuits includes means for removing a flag from the stream corresponding incoming when two consecutive flags are present in said incoming stream and when the memory has

  its filling level which is higher than a maximum filling level.

  According to another additional characteristic, said means consist of a shift register supplied by said incoming stream, of a comparator for comparing the byte contained in said shift register with said sequence of bits constituting said flag and for delivering to a write control unit a flag signal when there is a match, said write control unit prohibiting writing to said memory when two flag signals have been transmitted consecutively and when the memory has its level of filling which is above a level of

maximum filling.

  According to another additional characteristic, the frames of said oriented protocol being delimited by flags made up of a determined bit sequence, each of said input circuits includes means for inserting a flag into stream 20 intended to form the corresponding outgoing stream when two consecutive flags are present in said stream and when the memory has its fill level which is

  below a minimum filling level.

  According to another additional characteristic, said means consist of two shift registers connected in series at the output of the memory, a comparator 25 for comparing the two bytes contained in said shift registers with twice said sequence of bits constituting said flag and for supplying a read control signal with a consecutive flag signal when there is a match, said read control unit prohibiting reading of said memory when two flag signals have been transmitted consecutively and when the memory has its level filling which is below a minimum filling level and

  loading in the first or each of said registers the value of said flag.

  According to another additional characteristic, said transmission system comprises a time base which is designed to deliver an input selection signal k to said multiplexer and an input circuit selection signal to each

of said input circuits.

  According to another additional characteristic, said time base is provided

  to deliver said internal clock signal to each of said input circuits.

  The features of the invention mentioned above, as well as others,

  will appear more clearly on reading the following description of an exemplary embodiment, said description being made in relation to the attached drawings, among

  which: Fig. 1 is a diagram showing the structure of an HDLC type frame, FIG. 2 is a block diagram of a transmission system according to the present invention, and FIG. 3 and a block diagram of an input circuit of a

  transmission according to the present invention.

  A transmission system according to the present invention, such as that shown in FIG. 2, consists essentially of a plurality of input circuits l to bn whose inputs are provided to be able to receive plesiochronous data streams FI to F, and of a time multiplexer 2 each of whose inputs is connected to an output an input circuit li (1 = 1 to n) and whose output is on a link 3

  to a central processing unit 4 o, the data of the flows FI to F are processed.

  The essential function of the input circuits 11 to 1, is to align the plesiochronous data streams FI to Fn on the same time base and on the same frequency. As for multiplexer 2, it is to temporally multiplex the plesiochronous data streams FI to Fn once these are aligned. On the link 3, therefore, time frames circulate each consisting of a plurality of time intervals IT1 to 25 ITm of length one byte, in each of which there are each of the bytes constituting the data of a plesiochronous flow FI to Fn. The number m of time intervals IT1 (i = 1 to m) is equal to the number of plesiochronous flows FI to F ,. It can also be higher. In this case, the time intervals ITi for i greater than n but less than or equal to m are filled with bits at 1. A frame alignment word 30 is included in each time frame. It can be, like the frame called El

  complies with ITU G.732 standard, from the first ITo time interval.

  In addition, the flow of time frames is accompanied by a signal

synchronization on a link 5.

  The input circuits 11 to i, and the time multiplexer 2 are controlled by a

  same clock 5. The time base 6 delivers a word k (k = 1 to n) which is used by the multiplexer 2 to select the output of the kth input circuit 1k and deliver on its output and the link 3 the flow Fk. It also delivers a control signal Rk at the same time as the word k to command the device 1k to deliver on its output a byte of the stream Fk.

  The central processing unit 4 can, after processing, deliver each of the streams F'1 to F'n, processed on a link 6, possibly accompanied by a link 7 for synchronization signals, also carrying a structural time frame identical to 10 that present on link 3, this frame being demultiplexed in a

  demultiplexer 5 whose outputs respectively deliver the flows F ', to F'n.

  There is shown in FIG. 3 is a block diagram of an input circuit 10 constituting one of the devices 11 to 1, of the system shown in FIG. 2. It receives a plesiochronous data stream F and delivers, byte after byte, the data Ds of this stream. 15 More precisely, the flow F consists of a data flow Fe and a clock signal

  This is clocked at the bit level of the data of the flow Fe.

  The data From is supplied to a shift register 11 of length one byte and

  clocked by the clock signal Ce. Each byte is then stored bit by bit in a buffer memory 12 of FIFO type (first input - first output). To do this, the memory 12 is also clocked by the clock signal Ce.

  A comparator 13 compares the byte which is contained in the shift register 11 with the sequence of bits 7Eh, flag of the frames carrying the data of the flow F. If the byte contained in the shift register 11 corresponds to the sequence of bits 7Eh,

  then a flag signal sf is transmitted to a write control unit 14.

  The function of the write control unit 14 is as follows. On reception of the flag signal sf, it checks whether the previous byte also corresponded to a sequence 7Eh. If this were not the case, it authorizes, by the signal wren, the writing in the memory 12 of the byte which is present in the shift register 11. If this was the case on the other hand, it reads the level filling the memory 12 which it receives with a signal 30 of level p which the latter delivers. It then compares this filling level with a maximum level pmax threshold. If the filling level p is lower than the threshold level pmax, it authorizes, by the signal wren, the writing in the memory 12 of the byte which is present in the shift register 11. On the other hand, if the filling level p is greater than the threshold level pmax, it inhibits, by the same signal wren, the process

writing to memory 12.

  Thus, when two consecutive flags are detected in the incoming data stream Fe, one of these flags is deleted when the FIFO memory 12 has a filling level p greater than a maximum filling level threshold pmax. When the memory 12 is commanded to read, the bytes which are delivered are supplied, bit by bit, to a first shift register 15 which again delivers them to a second shift register 16. The memory 12 as well as the shift registers 15 and 16 are clocked by means of the clock signal Cs which is delivered by the time base 5 (see Fig. 2). The nominal frequency of this clock signal Cs is identical to the nominal frequency of the signal Ce, but the actual frequency may differ from it

  little. It is in this that the flow F is a plesiochronous flow.

  The memory 12 is commanded to read by a signal ren delivered by a read control unit 17. This signal ren is delivered by said unit 17 when the latter 15 receives the control signal Ck coming from the time base 5, as this has been explained above in connection with FIG. 1. As the bits delivered by memory 12 are read, the bits contained in registers 15 and 16 are shifted

  to the right and are then delivered to the data output Ds.

  The bytes which are present in the two shift registers 15 and 16 are applied to the inputs of a comparator 18 which compares them to the sequence 7E7Eh, ie two consecutive flags of the frame of the incoming stream. When the two bytes present in the two shift registers 15 and 16 are equal to 7E, the comparator 18 delivers to the read control unit 17 a signal sff relating to two consecutive flags. At this moment, this unit 17 reads the filling level p of the memory 12 and compares this filling level p with a filling level pmin. If the level p is higher than the level pmin, it authorizes, by the signal ren, the reading of the memory 12. On the other hand, if the level p is lower than the level pmin, it inhibits, by the same signal ren, the process of reading from memory 12 while the bits of shift registers 15 and 16 are shifted to the right. Consequently, the bits of register 16 are delivered 30 bit after bit on the data output Ds and the bits of register 15 are transferred into register 16. At the end of this shifting process, the read control unit 17 performs the loading of two bytes 7E respectively in the shift registers

  and 16 (in register 16 would suffice).

  Thus, when two consecutive flags are detected on the data stream intended for the data output Ds, a new flag is inserted if the FIFO memory has

  its filling level which is lower than a lower filling threshold level.

  As mentioned in the preamble to this description, the plesiochronous flows 5 at the input of each of the input circuits 11 to in originate from the communication channels, called DCCs (Data Communication Channel) present in a synchronous frame, such as an SDH or SONET frame, on a port of synchronous communication equipment. It has been shown that taking into account the frequency tolerances imposed by the SDH standard, the memory 12 with a capacity of 8 bytes, a minimum level pmin of 2 bytes and a

  pmax maximum level of 6 bytes could be fine.

Claims (7)

  1) System for transmitting a plurality of plesiochronous flows to a unit   central processing unit, such as the flows transported by frames according to a bit-oriented protocol, such as the so-called HDLC protocol, the data of the flows FI to F, being processed in said central processing unit (4), characterized in that '' it consists of a plurality of input circuits (11 to in,) whose inputs are provided to be able to receive plesiochronous data streams (Fi to Fn) and a time multiplexer (2) each of which inputs is connected to an output of an input circuit (l1; i = 1 to n) and whose output is on a link (3) to said central processing unit (4), the input circuits (11 1,) being provided for aligning the plesiochronous data streams (FI to Fn,) 10 on the same time base and on the same frequency.   2) Transmission system according to claim 1, the frames of said bit-oriented protocol being accompanied by a clock signal, characterized in that it comprises a memory (12) of the FIFO type provided for, on the one hand, enter the bytes from the incoming stream (Fe) at the rate of the clock signal accompanying said incoming stream (Fe) and, on the other hand, output said bytes in order to deliver them on the output of said device to   the cadence of the clock signal delivered by an internal clock (5).   3) Transmission system according to claim 2, the frames of said bit-oriented protocol being delimited by flags consisting of a determined bit sequence, characterized in that each of said input circuits (11 to In) comprises means to remove a flag from the corresponding incoming flow (Fe) when two consecutive flags are present in said incoming flow (Fe) and when the memory (12) has its filling level (p) which is greater than a filling level maximum (pmax).   4) Transmission system according to claim 3, characterized in that said means consist of a shift register (11) supplied by said incoming flow (Fe), a comparator (13) for comparing the byte contained in said shift register (11) with said sequence of bits constituting said flag and for outputting to a write control unit (14) a flag signal (sf) when there is a match, said control unit writing (14) prohibiting writing to said memory (12) when two flag signals have been transmitted consecutively and when the memory (12) has its filling level (p) which is greater than a level maximum filling (pmax).   ) Transmission system according to one of claims 2 to 4, the frames of said   bit-oriented protocol being delimited by flags consisting of a determined bit sequence, characterized in that each of said input circuits (11 to 1,) comprises means for inserting a flag into the flow intended to form the outgoing flow 5 corresponding when two consecutive flags are present in said stream and when the memory (12) has its filling level (p) which is less than a level of minimum filling (pmin).   6) Transmission system according to claim 5, characterized in that said means consist of two shift registers (15 and 16) connected in series at the output of the memory (12), a comparator for comparing the two bytes contained in said shift registers (15 and 16) with twice said sequence of bits constituting said flag and for outputting to a read control unit (17) a consecutive flag signal (sff) when there is a match, said unit read control (17) prohibiting the reading of said memory (12) when two flag signals have been transmitted consecutively and when the memory (12) has its level of   filling (p) which is lower than a minimum filling level (pmin) and loading in the first or each of said registers (15 and 16) the value of said flag.   7) Transmission system according to one of the preceding claims,   characterized in that it comprises a time base (5) which is designed to deliver an input selection signal k to said multiplexer (2) and a circuit selection signal   input (Ck) to each of said input circuits (h1 to ln).   8) Transmission system according to claim 7, characterized in that said time base (5) is provided for delivering said internal clock signal (Cs) to each of said input circuits (11 to 1,)