FR2666450B1 - - Google Patents

Info

Publication number
FR2666450B1
FR2666450B1 FR9100086A FR9100086A FR2666450B1 FR 2666450 B1 FR2666450 B1 FR 2666450B1 FR 9100086 A FR9100086 A FR 9100086A FR 9100086 A FR9100086 A FR 9100086A FR 2666450 B1 FR2666450 B1 FR 2666450B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9100086A
Other languages
French (fr)
Other versions
FR2666450A1 (fr
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of FR2666450A1 publication Critical patent/FR2666450A1/fr
Application granted granted Critical
Publication of FR2666450B1 publication Critical patent/FR2666450B1/fr
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/01Manufacture or treatment
    • H10D10/051Manufacture or treatment of vertical BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/133Emitter regions of BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/40Vertical BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0113Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0112Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
FR9100086A 1990-09-04 1991-01-04 Procede pour fabriquer un transistor bipolaire a emetteurs multiples. Granted FR2666450A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900013935A KR920007124A (ko) 1990-09-04 1990-09-04 폴리 에미터 바이폴라 트랜지스터의 제조방법

Publications (2)

Publication Number Publication Date
FR2666450A1 FR2666450A1 (fr) 1992-03-06
FR2666450B1 true FR2666450B1 (https=) 1993-02-26

Family

ID=19303215

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9100086A Granted FR2666450A1 (fr) 1990-09-04 1991-01-04 Procede pour fabriquer un transistor bipolaire a emetteurs multiples.

Country Status (6)

Country Link
JP (1) JPH0629302A (https=)
KR (1) KR920007124A (https=)
DE (1) DE4103594A1 (https=)
FR (1) FR2666450A1 (https=)
GB (1) GB2247780A (https=)
IT (1) IT1245092B (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4240738A1 (en) * 1992-12-03 1993-08-26 Siemens Ag Bipolar transistor prodn. for long service life - by forming base in surface of substrate, short term temp. adjusting, and forming emitter
JPH09500760A (ja) * 1993-07-12 1997-01-21 ナショナル・セミコンダクター・コーポレイション ヒ素注入エミッタを有する半導体デバイスの製造プロセス
KR19980054454A (ko) * 1996-12-27 1998-09-25 김영환 폴리실키콘층 형성 방법
US6093613A (en) * 1998-02-09 2000-07-25 Chartered Semiconductor Manufacturing, Ltd Method for making high gain lateral PNP and NPN bipolar transistor compatible with CMOS for making BICMOS circuits
KR100382725B1 (ko) * 2000-11-24 2003-05-09 삼성전자주식회사 클러스터화된 플라즈마 장치에서의 반도체소자의 제조방법
US7737049B2 (en) 2007-07-31 2010-06-15 Qimonda Ag Method for forming a structure on a substrate and device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0062725B1 (de) * 1981-04-14 1984-09-12 Deutsche ITT Industries GmbH Verfahren zum Herstellen eines integrierten Planartransistors
US4432809A (en) * 1981-12-31 1984-02-21 International Business Machines Corporation Method for reducing oxygen precipitation in silicon wafers
DE3304642A1 (de) * 1983-02-10 1984-08-16 Siemens AG, 1000 Berlin und 8000 München Integrierte halbleiterschaltung mit bipolartransistor-strukturen und verfahren zu ihrer herstellung
EP0170250B1 (en) * 1984-07-31 1990-10-24 Kabushiki Kaisha Toshiba Bipolar transistor and method for producing the bipolar transistor
KR880000483B1 (ko) * 1985-08-05 1988-04-07 재단법인 한국전자통신 연구소 반도체소자의 제조방법
US4693782A (en) * 1985-09-06 1987-09-15 Matsushita Electric Industrial Co., Ltd. Fabrication method of semiconductor device
EP0239825B1 (de) * 1986-03-21 1993-08-25 Siemens Aktiengesellschaft Verfahren zur Herstellung einer Bipolartransistorstruktur für Höchstgeschwindigkeitsschaltung
JPS6353928A (ja) * 1986-08-22 1988-03-08 Anelva Corp ドライエツチング方法
US4839302A (en) * 1986-10-13 1989-06-13 Matsushita Electric Industrial Co., Ltd. Method for fabricating bipolar semiconductor device
JPS63182860A (ja) * 1987-01-26 1988-07-28 Toshiba Corp 半導体装置とその製造方法
JP2654011B2 (ja) * 1987-03-31 1997-09-17 株式会社東芝 半導体装置の製造方法
JPH01157565A (ja) * 1987-12-14 1989-06-20 Nec Corp Bi−MOS集積回路装置の製造方法
JPH0736389B2 (ja) * 1988-11-10 1995-04-19 三菱電機株式会社 半導体装置の電極配線の形成方法

Also Published As

Publication number Publication date
KR920007124A (ko) 1992-04-28
ITMI910068A0 (it) 1991-01-11
DE4103594A1 (de) 1992-03-05
GB9100672D0 (en) 1991-02-27
IT1245092B (it) 1994-09-13
ITMI910068A1 (it) 1992-07-11
FR2666450A1 (fr) 1992-03-06
GB2247780A (en) 1992-03-11
JPH0629302A (ja) 1994-02-04

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Legal Events

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