FR2657171A1 - Circuit de test a grande echelle d'integration lsi. - Google Patents

Circuit de test a grande echelle d'integration lsi. Download PDF

Info

Publication number
FR2657171A1
FR2657171A1 FR9100438A FR9100438A FR2657171A1 FR 2657171 A1 FR2657171 A1 FR 2657171A1 FR 9100438 A FR9100438 A FR 9100438A FR 9100438 A FR9100438 A FR 9100438A FR 2657171 A1 FR2657171 A1 FR 2657171A1
Authority
FR
France
Prior art keywords
lsi
circuit
exclusive
test
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR9100438A
Other languages
English (en)
French (fr)
Other versions
FR2657171B1 (US07968547-20110628-C00004.png
Inventor
Nasu Yasuyuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2657171A1 publication Critical patent/FR2657171A1/fr
Application granted granted Critical
Publication of FR2657171B1 publication Critical patent/FR2657171B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/006—Identification

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
FR9100438A 1990-01-17 1991-01-16 Circuit de test a grande echelle d'integration lsi. Granted FR2657171A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008805A JPH03211481A (ja) 1990-01-17 1990-01-17 Ｌｓｉテスト回路

Publications (2)

Publication Number Publication Date
FR2657171A1 true FR2657171A1 (fr) 1991-07-19
FR2657171B1 FR2657171B1 (US07968547-20110628-C00004.png) 1994-12-16

Family

ID=11703058

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9100438A Granted FR2657171A1 (fr) 1990-01-17 1991-01-16 Circuit de test a grande echelle d'integration lsi.

Country Status (3)

Country Link
US (1) US5442301A (US07968547-20110628-C00004.png)
JP (1) JPH03211481A (US07968547-20110628-C00004.png)
FR (1) FR2657171A1 (US07968547-20110628-C00004.png)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7591781B2 (en) * 2002-07-15 2009-09-22 Olympus Corporation Endoscope system with insertion direction changing guides
GB0318487D0 (en) * 2003-08-07 2003-09-10 Ibm On-chip diagnostic arrangement and method
US7501832B2 (en) * 2005-02-28 2009-03-10 Ridgetop Group, Inc. Method and circuit for the detection of solder-joint failures in a digital electronic package
KR20140002163A (ko) * 2012-06-28 2014-01-08 에스케이하이닉스 주식회사 집적회로 칩 및 메모리 장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0008380A1 (en) * 1978-08-18 1980-03-05 International Business Machines Corporation Electronic circuit assembly for testing module interconnections
US4286173A (en) * 1978-03-27 1981-08-25 Hitachi, Ltd. Logical circuit having bypass circuit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961254A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
US4220917A (en) * 1978-07-31 1980-09-02 International Business Machines Corporation Test circuitry for module interconnection network
US4556840A (en) * 1981-10-30 1985-12-03 Honeywell Information Systems Inc. Method for testing electronic assemblies
JPS58115828A (ja) * 1981-12-29 1983-07-09 Fujitsu Ltd 半導体集積回路
US4546472A (en) * 1983-01-27 1985-10-08 Intel Corporation Method and means for testing integrated circuits
JPS6088370A (ja) * 1983-10-20 1985-05-18 Toshiba Corp 論理回路
JPH0691140B2 (ja) * 1986-07-11 1994-11-14 日本電気株式会社 半導体集積回路
US4782283A (en) * 1986-08-22 1988-11-01 Aida Corporation Apparatus for scan testing CMOS integrated systems
JPH0820967B2 (ja) * 1987-09-25 1996-03-04 三菱電機株式会社 集積回路
US4929889A (en) * 1988-06-13 1990-05-29 Digital Equipment Corporation Data path chip test architecture
US4862072A (en) * 1988-09-08 1989-08-29 General Electric Company Distributed access serial port test arrangement for integrated circuits
US5014226A (en) * 1988-09-29 1991-05-07 Lsi Logic Corporation Method and apparatus for predicting the metastable behavior of logic circuits
US4949341A (en) * 1988-10-28 1990-08-14 Motorola Inc. Built-in self test method for application specific integrated circuit libraries

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4286173A (en) * 1978-03-27 1981-08-25 Hitachi, Ltd. Logical circuit having bypass circuit
EP0008380A1 (en) * 1978-08-18 1980-03-05 International Business Machines Corporation Electronic circuit assembly for testing module interconnections

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN. vol. 30, no. 7, Décembre 1987, NEW YORK US pages 188 - 190 'New approach to level sensitive scan design testing' *
IBM TECHNICAL DISCLOSURE BULLETIN. vol. 31, no. 3, Août 1988, NEW YORK US pages 1 - 3 'Automatic test method for LSI module' *

Also Published As

Publication number Publication date
US5442301A (en) 1995-08-15
FR2657171B1 (US07968547-20110628-C00004.png) 1994-12-16
JPH03211481A (ja) 1991-09-17

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