FR2623349A1 - Dispositif de retard d'au moins un train de donnees binaires a haut debit - Google Patents

Dispositif de retard d'au moins un train de donnees binaires a haut debit Download PDF

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Publication number
FR2623349A1
FR2623349A1 FR8715945A FR8715945A FR2623349A1 FR 2623349 A1 FR2623349 A1 FR 2623349A1 FR 8715945 A FR8715945 A FR 8715945A FR 8715945 A FR8715945 A FR 8715945A FR 2623349 A1 FR2623349 A1 FR 2623349A1
Authority
FR
France
Prior art keywords
registers
fifo
signal
write
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR8715945A
Other languages
English (en)
French (fr)
Inventor
Michel Le Calvez
Michel Peruyero
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Thomson Faisceaux Hertziens SA
Original Assignee
Alcatel Thomson Faisceaux Hertziens SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Thomson Faisceaux Hertziens SA filed Critical Alcatel Thomson Faisceaux Hertziens SA
Priority to FR8715945A priority Critical patent/FR2623349A1/fr
Priority to EP88118949A priority patent/EP0317863B1/de
Priority to DE8888118949T priority patent/DE3881486T2/de
Priority to US07/273,469 priority patent/US5113368A/en
Priority to CA000583380A priority patent/CA1308449C/fr
Priority to JP63292246A priority patent/JPH01161915A/ja
Publication of FR2623349A1 publication Critical patent/FR2623349A1/fr
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Shift Register Type Memory (AREA)
  • Dram (AREA)
  • Pulse Circuits (AREA)
  • Communication Control (AREA)
FR8715945A 1987-11-18 1987-11-18 Dispositif de retard d'au moins un train de donnees binaires a haut debit Pending FR2623349A1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FR8715945A FR2623349A1 (fr) 1987-11-18 1987-11-18 Dispositif de retard d'au moins un train de donnees binaires a haut debit
EP88118949A EP0317863B1 (de) 1987-11-18 1988-11-14 Verzögerungsvorrichtung für zumindest einen digitalen Hochgeschwindigkeitsdatenstrom
DE8888118949T DE3881486T2 (de) 1987-11-18 1988-11-14 Verzoegerungsvorrichtung fuer zumindest einen digitalen hochgeschwindigkeitsdatenstrom.
US07/273,469 US5113368A (en) 1987-11-18 1988-11-17 Circuit for delaying at least one high bit rate binary data train
CA000583380A CA1308449C (fr) 1987-11-18 1988-11-17 Dispositif de retard d'au moins un train de donnees binaires a haut debit
JP63292246A JPH01161915A (ja) 1987-11-18 1988-11-18 少なくとも１つの高伝送速度二進データ列を遅延させる装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8715945A FR2623349A1 (fr) 1987-11-18 1987-11-18 Dispositif de retard d'au moins un train de donnees binaires a haut debit

Publications (1)

Publication Number Publication Date
FR2623349A1 true FR2623349A1 (fr) 1989-05-19

Family

ID=9356911

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8715945A Pending FR2623349A1 (fr) 1987-11-18 1987-11-18 Dispositif de retard d'au moins un train de donnees binaires a haut debit

Country Status (6)

Country Link
US (1) US5113368A (de)
EP (1) EP0317863B1 (de)
JP (1) JPH01161915A (de)
CA (1) CA1308449C (de)
DE (1) DE3881486T2 (de)
FR (1) FR2623349A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0394599B1 (de) * 1989-04-28 1994-07-20 International Business Machines Corporation Synchronisierschaltung für Datenüberträge zwischen zwei mit unterschiedlicher Geschwindigkeit arbeitenden Geräten
US5224213A (en) * 1989-09-05 1993-06-29 International Business Machines Corporation Ping-pong data buffer for transferring data from one data bus to another data bus
EP0483441B1 (de) * 1990-11-02 1998-01-14 STMicroelectronics S.r.l. System zur Speicherung von Daten auf FIFO-Basis
JPH087715B2 (ja) * 1990-11-15 1996-01-29 インターナショナル・ビジネス・マシーンズ・コーポレイション データ処理装置及びアクセス制御方法
FR2682192B1 (fr) * 1991-10-03 1993-11-12 Etat Francais Delegue Armement Dispositif pour generer un retard sur un signal numerique.
US5282271A (en) * 1991-10-30 1994-01-25 I-Cube Design Systems, Inc. I/O buffering system to a programmable switching apparatus
USH1507H (en) * 1993-04-23 1995-12-05 The United States Of America As Represented By The Secretary Of The Navy Demand assigned multiple access (DAMA) device controller interface
CN1295685A (zh) * 1998-06-17 2001-05-16 诺基亚网络有限公司 连接以不同时钟速度速率工作的设备的接口装置,和操作该接口的方法
JP4547198B2 (ja) * 2004-06-30 2010-09-22 富士通株式会社 演算装置、演算装置の制御方法、プログラム及びコンピュータ読取り可能記録媒体
US8037337B2 (en) * 2007-11-28 2011-10-11 International Business Machines Corporation Structures including circuits for noise reduction in digital systems
JP6015514B2 (ja) * 2013-03-25 2016-10-26 富士通株式会社 データ記憶装置及びデータ記憶方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3736568A (en) * 1970-02-18 1973-05-29 Diginetics Inc System for producing a magnetically recorded digitally encoded record in response to external signals
EP0018518A1 (de) * 1979-04-30 1980-11-12 International Business Machines Corporation Pufferspeichervorrichtung und Datenwegkonzentrator mit dieser Pufferspeichervorrichtung
GB2086623A (en) * 1980-09-19 1982-05-12 Hitachi Ltd First-in first-out storage and processing unit making use thereof
JPS6059433A (ja) * 1983-09-10 1985-04-05 Fujitsu Ltd バツフア制御回路
US4546444A (en) * 1983-03-15 1985-10-08 E. I. Du Pont De Nemours And Company Data compression interface having parallel memory architecture

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3736568A (en) * 1970-02-18 1973-05-29 Diginetics Inc System for producing a magnetically recorded digitally encoded record in response to external signals
EP0018518A1 (de) * 1979-04-30 1980-11-12 International Business Machines Corporation Pufferspeichervorrichtung und Datenwegkonzentrator mit dieser Pufferspeichervorrichtung
GB2086623A (en) * 1980-09-19 1982-05-12 Hitachi Ltd First-in first-out storage and processing unit making use thereof
US4546444A (en) * 1983-03-15 1985-10-08 E. I. Du Pont De Nemours And Company Data compression interface having parallel memory architecture
JPS6059433A (ja) * 1983-09-10 1985-04-05 Fujitsu Ltd バツフア制御回路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN, vol. 9, no. 190 (P-378)[1913], 7 août 1985; & JP-A-60 59 433 (FUJITSU K.K.) 05-04-1985 *

Also Published As

Publication number Publication date
DE3881486T2 (de) 1993-09-16
US5113368A (en) 1992-05-12
EP0317863A1 (de) 1989-05-31
JPH01161915A (ja) 1989-06-26
DE3881486D1 (de) 1993-07-08
CA1308449C (fr) 1992-10-06
EP0317863B1 (de) 1993-06-02

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