DE3881486D1 - Verzoegerungsvorrichtung fuer zumindest einen digitalen hochgeschwindigkeitsdatenstrom. - Google Patents
Verzoegerungsvorrichtung fuer zumindest einen digitalen hochgeschwindigkeitsdatenstrom.Info
- Publication number
- DE3881486D1 DE3881486D1 DE8888118949T DE3881486T DE3881486D1 DE 3881486 D1 DE3881486 D1 DE 3881486D1 DE 8888118949 T DE8888118949 T DE 8888118949T DE 3881486 T DE3881486 T DE 3881486T DE 3881486 D1 DE3881486 D1 DE 3881486D1
- Authority
- DE
- Germany
- Prior art keywords
- speed data
- delay device
- data current
- digital high
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Shift Register Type Memory (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Communication Control (AREA)
- Pulse Circuits (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8715945A FR2623349A1 (fr) | 1987-11-18 | 1987-11-18 | Dispositif de retard d'au moins un train de donnees binaires a haut debit |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3881486D1 true DE3881486D1 (de) | 1993-07-08 |
DE3881486T2 DE3881486T2 (de) | 1993-09-16 |
Family
ID=9356911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8888118949T Expired - Fee Related DE3881486T2 (de) | 1987-11-18 | 1988-11-14 | Verzoegerungsvorrichtung fuer zumindest einen digitalen hochgeschwindigkeitsdatenstrom. |
Country Status (6)
Country | Link |
---|---|
US (1) | US5113368A (de) |
EP (1) | EP0317863B1 (de) |
JP (1) | JPH01161915A (de) |
CA (1) | CA1308449C (de) |
DE (1) | DE3881486T2 (de) |
FR (1) | FR2623349A1 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE68916945T2 (de) * | 1989-04-28 | 1995-03-16 | Ibm | Synchronisierschaltung für Datenüberträge zwischen zwei mit unterschiedlicher Geschwindigkeit arbeitenden Geräten. |
US5224213A (en) * | 1989-09-05 | 1993-06-29 | International Business Machines Corporation | Ping-pong data buffer for transferring data from one data bus to another data bus |
DE69031948T2 (de) * | 1990-11-02 | 1998-04-23 | St Microelectronics Srl | System zur Speicherung von Daten auf FIFO-Basis |
JPH087715B2 (ja) * | 1990-11-15 | 1996-01-29 | インターナショナル・ビジネス・マシーンズ・コーポレイション | データ処理装置及びアクセス制御方法 |
FR2682192B1 (fr) * | 1991-10-03 | 1993-11-12 | Etat Francais Delegue Armement | Dispositif pour generer un retard sur un signal numerique. |
US5282271A (en) * | 1991-10-30 | 1994-01-25 | I-Cube Design Systems, Inc. | I/O buffering system to a programmable switching apparatus |
USH1507H (en) * | 1993-04-23 | 1995-12-05 | The United States Of America As Represented By The Secretary Of The Navy | Demand assigned multiple access (DAMA) device controller interface |
AU756039B2 (en) * | 1998-06-17 | 2003-01-02 | Nokia Corporation | An interface apparatus for connecting devices operating at different clock rates, and a method of operating the interface |
JP4547198B2 (ja) * | 2004-06-30 | 2010-09-22 | 富士通株式会社 | 演算装置、演算装置の制御方法、プログラム及びコンピュータ読取り可能記録媒体 |
US8037337B2 (en) * | 2007-11-28 | 2011-10-11 | International Business Machines Corporation | Structures including circuits for noise reduction in digital systems |
JP6015514B2 (ja) * | 2013-03-25 | 2016-10-26 | 富士通株式会社 | データ記憶装置及びデータ記憶方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3736568A (en) * | 1970-02-18 | 1973-05-29 | Diginetics Inc | System for producing a magnetically recorded digitally encoded record in response to external signals |
US4298954A (en) * | 1979-04-30 | 1981-11-03 | International Business Machines Corporation | Alternating data buffers when one buffer is empty and another buffer is variably full of data |
JPS6057090B2 (ja) * | 1980-09-19 | 1985-12-13 | 株式会社日立製作所 | データ記憶装置およびそれを用いた処理装置 |
US4546444A (en) * | 1983-03-15 | 1985-10-08 | E. I. Du Pont De Nemours And Company | Data compression interface having parallel memory architecture |
JPS6059433A (ja) * | 1983-09-10 | 1985-04-05 | Fujitsu Ltd | バツフア制御回路 |
-
1987
- 1987-11-18 FR FR8715945A patent/FR2623349A1/fr active Pending
-
1988
- 1988-11-14 DE DE8888118949T patent/DE3881486T2/de not_active Expired - Fee Related
- 1988-11-14 EP EP88118949A patent/EP0317863B1/de not_active Expired - Lifetime
- 1988-11-17 US US07/273,469 patent/US5113368A/en not_active Expired - Fee Related
- 1988-11-17 CA CA000583380A patent/CA1308449C/fr not_active Expired - Lifetime
- 1988-11-18 JP JP63292246A patent/JPH01161915A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPH01161915A (ja) | 1989-06-26 |
EP0317863B1 (de) | 1993-06-02 |
EP0317863A1 (de) | 1989-05-31 |
CA1308449C (fr) | 1992-10-06 |
DE3881486T2 (de) | 1993-09-16 |
FR2623349A1 (fr) | 1989-05-19 |
US5113368A (en) | 1992-05-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |