FR2535506B1 - Dispositif d'alignement bidirectionnel de multiplets de donnees pour memoire a acces aleatoire et procede pour sa mise en oeuvre - Google Patents

Dispositif d'alignement bidirectionnel de multiplets de donnees pour memoire a acces aleatoire et procede pour sa mise en oeuvre

Info

Publication number
FR2535506B1
FR2535506B1 FR8317424A FR8317424A FR2535506B1 FR 2535506 B1 FR2535506 B1 FR 2535506B1 FR 8317424 A FR8317424 A FR 8317424A FR 8317424 A FR8317424 A FR 8317424A FR 2535506 B1 FR2535506 B1 FR 2535506B1
Authority
FR
France
Prior art keywords
implementation
random access
access memory
multiple data
bidirectional alignment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8317424A
Other languages
English (en)
Other versions
FR2535506A1 (fr
Inventor
Brian D Morrison
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Publication of FR2535506A1 publication Critical patent/FR2535506A1/fr
Application granted granted Critical
Publication of FR2535506B1 publication Critical patent/FR2535506B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
FR8317424A 1982-11-01 1983-11-02 Dispositif d'alignement bidirectionnel de multiplets de donnees pour memoire a acces aleatoire et procede pour sa mise en oeuvre Expired FR2535506B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/438,142 US4507731A (en) 1982-11-01 1982-11-01 Bidirectional data byte aligner

Publications (2)

Publication Number Publication Date
FR2535506A1 FR2535506A1 (fr) 1984-05-04
FR2535506B1 true FR2535506B1 (fr) 1988-11-10

Family

ID=23739412

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8317424A Expired FR2535506B1 (fr) 1982-11-01 1983-11-02 Dispositif d'alignement bidirectionnel de multiplets de donnees pour memoire a acces aleatoire et procede pour sa mise en oeuvre

Country Status (7)

Country Link
US (1) US4507731A (fr)
JP (1) JPS5998262A (fr)
CA (1) CA1205207A (fr)
DE (1) DE3339645A1 (fr)
FR (1) FR2535506B1 (fr)
GB (1) GB2131578B (fr)
NL (1) NL8303734A (fr)

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US4683534A (en) * 1985-06-17 1987-07-28 Motorola, Inc. Method and apparatus for interfacing buses of different sizes
DE3635074A1 (de) * 1986-10-15 1988-04-21 Itt Ind Gmbh Deutsche Speicheranordnung mit einem speicherarray
US4959771A (en) * 1987-04-10 1990-09-25 Prime Computer, Inc. Write buffer for a digital processing system
US4954983A (en) * 1987-10-13 1990-09-04 Tektronix, Inc. Data driver for multiple mode buffered processor-peripheral data transfer with selective return of data to processor
US5073969A (en) * 1988-08-01 1991-12-17 Intel Corporation Microprocessor bus interface unit which changes scheduled data transfer indications upon sensing change in enable signals before receiving ready signal
US4979148A (en) * 1988-12-09 1990-12-18 International Business Machines Corporation Increasing options in mapping ROM in computer memory space
US5201043A (en) * 1989-04-05 1993-04-06 Intel Corporation System using both a supervisor level control bit and a user level control bit to enable/disable memory reference alignment checking
US6038584A (en) * 1989-11-17 2000-03-14 Texas Instruments Incorporated Synchronized MIMD multi-processing system and method of operation
US5168561A (en) * 1990-02-16 1992-12-01 Ncr Corporation Pipe-line method and apparatus for byte alignment of data words during direct memory access transfers
JP2606942B2 (ja) * 1990-02-22 1997-05-07 株式会社東芝 Ｄｍａコントローラ
US5442769A (en) * 1990-03-13 1995-08-15 At&T Corp. Processor having general registers with subdivisions addressable in instructions by register number and subdivision type
DE69227604T2 (de) * 1991-03-11 1999-06-24 Silicon Graphics Inc Mountain Rückwärts kompatible Rechnerarchitektur mit erweiterten Wortbreiten und Adressraum
US5861894A (en) * 1993-06-24 1999-01-19 Discovision Associates Buffer manager
US5699544A (en) * 1993-06-24 1997-12-16 Discovision Associates Method and apparatus for using a fixed width word for addressing variable width data
CA2145379C (fr) * 1994-03-24 1999-06-08 William P. Robbins Methode et dispositif d'adressage memoire
CA2145361C (fr) * 1994-03-24 1999-09-07 Martin William Sotheran Gestionnaire de tampons
TW321744B (fr) * 1994-04-01 1997-12-01 Ibm
US5687328A (en) * 1995-05-16 1997-11-11 National Semiconductor Corporation Method and apparatus for aligning data for transfer between a source memory and a destination memory over a multibit bus
DE69616718D1 (de) * 1995-05-26 2001-12-13 Nat Semiconductor Corp Vorrichtung und verfahren zur bestimmung von adressen fehlausgerichteter daten
US6119213A (en) * 1995-06-07 2000-09-12 Discovision Associates Method for addressing data having variable data width using a fixed number of bits for address and width defining fields
DE19525099C2 (de) * 1995-06-29 2002-09-19 Abb Patent Gmbh Verfahren zum Zugriff auf Speicherstellen
DE19525104A1 (de) * 1995-06-29 1997-01-09 Hartmann & Braun Ag Verfahren zum Adressieren von Speicherstellen
US6125435A (en) * 1995-09-13 2000-09-26 Lexar Media, Inc. Alignment of cluster address to block addresses within a semiconductor non-volatile mass storage memory
US6122717A (en) * 1996-06-17 2000-09-19 Integrated Device Technology, Inc. Methods and apparatus for a memory that supports a variable number of bytes per logical cell and a variable number of cells
US6523080B1 (en) 1996-07-10 2003-02-18 International Business Machines Corporation Shared bus non-sequential data ordering method and apparatus
US5995579A (en) * 1996-12-19 1999-11-30 Vlsi Technology, Inc. Barrel shifter, circuit and method of manipulating a bit pattern
US6078937A (en) * 1996-12-19 2000-06-20 Vlsi Technology, Inc. Barrel shifter, circuit and method of manipulating a bit pattern
US5961628A (en) * 1997-01-28 1999-10-05 Samsung Electronics Co., Ltd. Load and store unit for a vector processor
US7197625B1 (en) 1997-10-09 2007-03-27 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US5864703A (en) * 1997-10-09 1999-01-26 Mips Technologies, Inc. Method for providing extended precision in SIMD vector arithmetic operations
US7181484B2 (en) * 2001-02-21 2007-02-20 Mips Technologies, Inc. Extended-precision accumulation of multiplier output
US7599981B2 (en) * 2001-02-21 2009-10-06 Mips Technologies, Inc. Binary polynomial multiplier
US7162621B2 (en) 2001-02-21 2007-01-09 Mips Technologies, Inc. Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration
US7711763B2 (en) * 2001-02-21 2010-05-04 Mips Technologies, Inc. Microprocessor instructions for performing polynomial arithmetic operations
US6820186B2 (en) * 2001-03-26 2004-11-16 Sun Microsystems, Inc. System and method for building packets
US6912173B2 (en) * 2001-06-29 2005-06-28 Broadcom Corporation Method and system for fast memory access
EP3507803B1 (fr) * 2016-09-02 2024-04-10 Rambus Inc. Composant de mémoire à alignement de débit de données d'entrée/sortie

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US3602896A (en) * 1969-06-30 1971-08-31 Ibm Random access memory with flexible data boundaries
US3781812A (en) * 1971-06-28 1973-12-25 Burroughs Corp Addressing system responsive to a transfer vector for accessing a memory
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US4156905A (en) * 1974-02-28 1979-05-29 Ncr Corporation Method and apparatus for improving access speed in a random access memory
US4020470A (en) * 1975-06-06 1977-04-26 Ibm Corporation Simultaneous addressing of different locations in a storage unit
US4079451A (en) * 1976-04-07 1978-03-14 Honeywell Information Systems Inc. Word, byte and bit indexed addressing in a data processing system
US4099253A (en) * 1976-09-13 1978-07-04 Dynage, Incorporated Random access memory with bit or byte addressing capability
US4092728A (en) * 1976-11-29 1978-05-30 Rca Corporation Parallel access memory system
DE2656086C2 (de) * 1976-12-10 1986-08-28 Siemens AG, 1000 Berlin und 8000 München Rechenanlage
US4131940A (en) * 1977-07-25 1978-12-26 International Business Machines Corporation Channel data buffer apparatus for a digital data processing system
US4247920A (en) * 1979-04-24 1981-01-27 Tektronix, Inc. Memory access system
EP0032136B1 (fr) * 1980-01-08 1990-10-10 Honeywell Bull Inc. Système de mémoire
US4520439A (en) * 1981-01-05 1985-05-28 Sperry Corporation Variable field partial write data merge
CA1183275A (fr) * 1981-10-02 1985-02-26 Martin J. Schwartz Memoire a acces a plusieurs multiplets pour instructions et donnees de longueur variable
GB2117945A (en) * 1982-04-01 1983-10-19 Raytheon Co Memory data transfer

Also Published As

Publication number Publication date
JPS5998262A (ja) 1984-06-06
FR2535506A1 (fr) 1984-05-04
DE3339645A1 (de) 1984-07-12
GB2131578B (en) 1986-10-15
GB8328517D0 (en) 1983-11-23
NL8303734A (nl) 1984-06-01
US4507731A (en) 1985-03-26
CA1205207A (fr) 1986-05-27
GB2131578A (en) 1984-06-20

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