FR2529715A1 - Procede d'optimisation du dopage dans un transistor mos - Google Patents

Procede d'optimisation du dopage dans un transistor mos Download PDF

Info

Publication number
FR2529715A1
FR2529715A1 FR8211571A FR8211571A FR2529715A1 FR 2529715 A1 FR2529715 A1 FR 2529715A1 FR 8211571 A FR8211571 A FR 8211571A FR 8211571 A FR8211571 A FR 8211571A FR 2529715 A1 FR2529715 A1 FR 2529715A1
Authority
FR
France
Prior art keywords
ions
type
substrate
doping
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8211571A
Other languages
English (en)
French (fr)
Other versions
FR2529715B1 (cg-RX-API-DMAC10.html
Inventor
Pierre Jeuch
Thierry Bonnet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR8211571A priority Critical patent/FR2529715A1/fr
Priority to EP83401331A priority patent/EP0099787A1/fr
Priority to JP58118387A priority patent/JPS5921068A/ja
Publication of FR2529715A1 publication Critical patent/FR2529715A1/fr
Application granted granted Critical
Publication of FR2529715B1 publication Critical patent/FR2529715B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H10P30/21
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149Source or drain regions of field-effect devices
    • H10D62/151Source or drain regions of field-effect devices of IGFETs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351Substrate regions of field-effect devices
    • H10D62/357Substrate regions of field-effect devices of FETs
    • H10D62/364Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H10P30/204

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)
FR8211571A 1982-07-01 1982-07-01 Procede d'optimisation du dopage dans un transistor mos Granted FR2529715A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR8211571A FR2529715A1 (fr) 1982-07-01 1982-07-01 Procede d'optimisation du dopage dans un transistor mos
EP83401331A EP0099787A1 (fr) 1982-07-01 1983-06-28 Procédé d'optimisation du dopage dans un transistor MOS
JP58118387A JPS5921068A (ja) 1982-07-01 1983-07-01 Mosトランジスタにおけるド−ピング最適化方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8211571A FR2529715A1 (fr) 1982-07-01 1982-07-01 Procede d'optimisation du dopage dans un transistor mos

Publications (2)

Publication Number Publication Date
FR2529715A1 true FR2529715A1 (fr) 1984-01-06
FR2529715B1 FR2529715B1 (cg-RX-API-DMAC10.html) 1984-12-21

Family

ID=9275586

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8211571A Granted FR2529715A1 (fr) 1982-07-01 1982-07-01 Procede d'optimisation du dopage dans un transistor mos

Country Status (3)

Country Link
EP (1) EP0099787A1 (cg-RX-API-DMAC10.html)
JP (1) JPS5921068A (cg-RX-API-DMAC10.html)
FR (1) FR2529715A1 (cg-RX-API-DMAC10.html)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0255882A3 (de) * 1986-08-07 1990-05-30 Siemens Aktiengesellschaft npn-Bipolartransistor mit extrem flachen Emitter/Basis-Strukturen und Verfahren zu seiner Herstellung
US4889819A (en) * 1988-05-20 1989-12-26 International Business Machines Corporation Method for fabricating shallow junctions by preamorphizing with dopant of same conductivity as substrate
EP0359530A3 (en) * 1988-09-15 1991-01-02 Advanced Micro Devices, Inc. Capacitive reduction of junctions in a semiconductor device
DE69027312T2 (de) * 1989-03-02 1997-01-30 Thunderbird Tech Inc Feldeffekttransistor mit fermi-schwellenspannung

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2337428A1 (fr) * 1975-12-31 1977-07-29 Ibm Transistor a effet de champ a canal composite et procede de fabrication

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2337428A1 (fr) * 1975-12-31 1977-07-29 Ibm Transistor a effet de champ a canal composite et procede de fabrication

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
APPLIED PHYSICS LETTERS, volume 35, no. 8, octobre 1979 (NEW YORK, US) M. KOYANAGI et al. "Short-channel MOS FET's fabricated by self-aligned ion implantation and laser-annealing", pages 621-623 *
IBM TECHNICAL DISCLOSURE BULLETIN, volume 17, no. 4, septembre 1974 (NEW YORK; US) D.R. YOUNG "Metal-oxide semiconductor field-effect transistor structure", pages 1208-1209 *
IEEE ELECTRON DEVICES, volume ED-27, no. 8, août 1980 (NEW YORK, US) R.F. MOTTA et al. "Computer-aided device optimization for MOS/VLSI", pages 1559-1565 *
IEEE JOURNAL OF SOLID-STATE CIRCUITS, volume SC-14, no. 3, juin 1979 (NEW YORK; US) J. PEREIRA DE SOUZA et al. "A simplified self-aligned al-gate MOS technology for high performance depletion-logic circuits", pages 651-653 *

Also Published As

Publication number Publication date
FR2529715B1 (cg-RX-API-DMAC10.html) 1984-12-21
JPS5921068A (ja) 1984-02-02
EP0099787A1 (fr) 1984-02-01

Similar Documents

Publication Publication Date Title
JP2578204B2 (ja) 半導体デバイスの製造方法
KR0172793B1 (ko) 반도체소자의 제조방법
US4315781A (en) Method of controlling MOSFET threshold voltage with self-aligned channel stop
US6083846A (en) Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon
US6359310B1 (en) Shallow doped junctions with a variable profile gradation of dopants
FR2498812A1 (fr) Structure de transistors dans un circuit integre et son procede de fabrication
FR2577348A1 (fr) Procede de formation de regions de silicium isolees et de dispositifs a effet de champ sur un substrat de silicium
FR2481518A1 (fr) Procede de realisation d'un dispositif semiconducteur comportant des transistors a effet de champ complementaires
FR2735908A1 (fr) Dispositif a semiconducteurs comportant un transistor a effet de champ et son procede de fabrication
US6879007B2 (en) Low volt/high volt transistor
US20080268628A1 (en) N-type semiconductor component with improved dopant implantation profile and method of forming same
US5073509A (en) Blanket CMOS channel-stop implant
FR2529715A1 (fr) Procede d'optimisation du dopage dans un transistor mos
TWI234849B (en) Structure and method of controlling short-channel effect of very short channel MOSFET
CN1581451A (zh) 制造半导体器件的方法
US5700717A (en) Method of reducing contact resistance for semiconductor manufacturing processes using tungsten plugs
JPS5880851A (ja) 半導体装置とその製造方法
FR2482368A1 (fr) Operateur logique a injection par le substrat et son procede de fabrication
FR2742583A1 (fr) Transistor a effet de champ a grille isolee et a canal diffuse
EP0158670A1 (en) Semiconductor integrated circuits containing complementary metal oxide semiconductor devices
US6613626B1 (en) Method of forming CMOS transistor having a deep sub-micron mid-gap metal gate
FR2786608A1 (fr) Procede de fabrication de circuits integres bicmos sur un substrat cmos classique
JPS6097663A (ja) 集積回路
EP1675182B1 (en) Image sensor pixel having a transfer gate formed from P+ or N+ doped polysilicon
US9406567B1 (en) Method for fabricating multiple transistor devices on a substrate with varying threshold voltages

Legal Events

Date Code Title Description
ST Notification of lapse