FR2529715A1 - METHOD FOR OPTIMIZING DOPING IN A MOS TRANSISTOR - Google Patents
METHOD FOR OPTIMIZING DOPING IN A MOS TRANSISTOR Download PDFInfo
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- FR2529715A1 FR2529715A1 FR8211571A FR8211571A FR2529715A1 FR 2529715 A1 FR2529715 A1 FR 2529715A1 FR 8211571 A FR8211571 A FR 8211571A FR 8211571 A FR8211571 A FR 8211571A FR 2529715 A1 FR2529715 A1 FR 2529715A1
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 150000002500 ions Chemical class 0.000 claims abstract description 38
- 238000002513 implantation Methods 0.000 claims abstract description 30
- -1 boron ions Chemical class 0.000 claims description 17
- 238000000137 annealing Methods 0.000 claims description 12
- 229910052796 boron Inorganic materials 0.000 claims description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- 229910052785 arsenic Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000010894 electron beam technology Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 241000288140 Gruiformes Species 0.000 description 1
- 241001676573 Minium Species 0.000 description 1
- 208000037656 Respiratory Sounds Diseases 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 206010037833 rales Diseases 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
L'INVENTION CONCERNE UN PROCEDE D'OPTIMISATION DU DOPAGE DANS UN TRANSISTOR MOS, CE TRANSISTOR COMPRENANT UN CANAL DEFINI, DANS UN SUBSTRAT SEMI-CONDUCTEUR DOPE 2, PAR UNE IMPLANTATION D'IONS APPARTENANT A UN PREMIER TYPE D'IONS DONNANT UN DOPAGE DU MEME TYPE D'IONS DONNANT UN DOPAGE DU MEME TYPE QUE CELUI DU SUBSTRAT 2, UNE SOURCE 4 ET UN DRAIN 6 DEFINIS, DANS LEDIT SUBSTRAT, PAR UNE IMPLANTATION D'IONS APPARTENANT A UN DEUXIEME TYPE D'IONS DONNANT UN DOPAGE DIFFERENT DE CELUI DU SUBSTRAT 2, ET UNE GRILLE 10 CARACTERISEE EN CE QUE L'ON REALISE, SOUS LA SOURCE 4 ET LE DRAIN 6 DU TRANSISTOR AU MOINS UNE IMPLANTATION D'IONS APPARTENANT AU DEUXIEME TYPE D'IONS DEFINISSANT DANS LE SUBSTRAT DEUX REGIONS LATERALES 16, 18, CETTE IMPLANTATION ETANT FAITE A UNE DOSE TELLE QU'ELLE COMPENSE LE DOPAGE DU SUBSTRAT 2 SANS EN INVERSER LE TYPE, LA GRILLE 10 DU TRANSISTOR SERVANT DE MASQUE A CETTE IMPLANTATION, ET EN CE QUE L'ON SOUMET LE SUBSTRAT 2 A UN RECUIT.THE INVENTION RELATES TO A METHOD FOR OPTIMIZING DOPING IN A MOS TRANSISTOR, THIS TRANSISTOR INCLUDING A DEFINED CHANNEL, IN A SEMICONDUCTOR DOPE 2 SUBSTRATE, BY AN IMPLANTATION OF IONS BELONGING TO A FIRST TYPE OF ION DOPING SAME TYPE OF IONS GIVING A DOPING OF THE SAME TYPE AS THAT OF SUBSTRATE 2, A SOURCE 4 AND A DRAIN 6 DEFINED, IN SUCH SUBSTRATE, BY AN IMPLANTATION OF IONS BELONGING TO A SECOND TYPE OF IONS GIVING A DIFFERENT DIFFERENT FROM THAT SUBSTRATE 2, AND A GRID 10 CHARACTERIZED IN THAT THERE IS REALIZED, UNDER SOURCE 4 AND DRAIN 6 OF THE TRANSISTOR AT LEAST ONE ION IMPLANTATION BELONGING TO THE SECOND TYPE OF ION DEFINING IN THE SUBSTRATE TWO SIDE REGIONS 16, 18, THIS IMPLANTATION BEING DONE SUCH AS IT COMPENSATES THE SUBSTRATE 2 DOPING WITHOUT INVERTING THE TYPE, THE GRID 10 OF THE TRANSISTOR SERVING AS A MASK FOR THIS IMPLANTATION, AND IN THAT THE SUBSTRATE 2 IS SUBMITTED TO A ANNUIT.
Description
La présente invention a pour objet un pro-The subject of the present invention is a pro-
cédé d'optimisation du dopage dans un transistor MOS (métal-oxydesemiconducteur). De plus en plus, on cherche à diminuer, par tous les moyens possibles, les dimensions des compo- yielded optimization of doping in a MOS (metal-oxide semiconductor) transistor. We are increasingly trying to reduce, by all possible means, the dimensions of the components.
sants élémentaires des circuits intégrés et en parti- basic health of integrated circuits and in particular
culier ceux des circuits comportant des transistors MOS Pour augmenter la densité d'intégration de-ces circuits, on cherche en particulier à diminuer la longueur du canal des transistors MOS, c'est-à-dire, la distance séparant la source et le drain de ces transistors. Afin d'éviter le perçage, c'est-à-dire une liaison entre la zone de charge d'espace de la source especially those of circuits comprising MOS transistors To increase the integration density of these circuits, we seek in particular to decrease the length of the channel of the MOS transistors, that is to say, the distance separating the source and the drain of these transistors. To avoid drilling, i.e. a connection between the space charge area of the source
et la zone de charge d'espace du drain de ces tran- and the space charge area of the drain of these trans-
sistors MOS, lors de la diminution de la longueur de leurs canaux, on implante, sous ces derniers, des ions donnant un dopage du même type que celui du substrat dans lequel on réalise le transistor; plus MOS sistors, when the length of their channels decreases, ions are implanted under these channels giving doping of the same type as that of the substrate in which the transistor is produced; more
on cherche à diminuer la longueur du canal d'un tran- we are trying to reduce the length of the channel by a
sistor MOS, plus la dose d'ions implantés sous le MOS sistor, the higher the dose of ions implanted under the
canal doit être élevée.channel should be high.
Malheureusement, l'augmentation d'un tel Unfortunately, the increase in such
dopage conduit à une augmentation des capacités para- doping leads to an increase in para-
sites entre la source, le drain et le substrat des transistors, du fait de la diminution de la largeur sites between the source, the drain and the substrate of the transistors, due to the reduction in width
des zones de charge d'espace affectant les caracté- space charge zones affecting the characteristics
ristiques électriques de ces derniers. electrical characteristics of the latter.
Afin d'améliorer les caractéristiques électriques des transistors MOS, l'une des méthodes In order to improve the electrical characteristics of MOS transistors, one of the methods
possible consisterait à augmenter le dopage du subs- possible would be to increase doping of the
trat dans la région de celui-ci située uniquement trat in the region thereof located only
sous la grille du transistor, de façon à ne pas aug- under the transistor gate, so as not to increase
menter le dopage dans les régions du substrat situées lie doping in the regions of the substrate located
en dessous de la source et du drain de ce transistor. below the source and the drain of this transistor.
La présente invention a Justement pour objet un procédé d'optimisation du dopage dans un transistor MOS permettant d'obtenir un tel profil de dopage Selon l'invention, ce profil de dopage est obtenu en-compensant, au niveau de la source et du drain du transistor MOS, le dopage du substrat sous The subject of the present invention is precisely a method of optimizing doping in a MOS transistor making it possible to obtain such a doping profile. According to the invention, this doping profile is obtained by compensating, at the level of the source and of the drain. of the MOS transistor, the doping of the substrate under
le canal de ce transistor.the channel of this transistor.
De façon plus précise, l'invention a pour objet un procédé d'optimisation du dopage dans un transistor MOS, ce transistor étant réalisé sur un More specifically, the invention relates to a method for optimizing doping in a MOS transistor, this transistor being produced on a
substrat en silicium dopé, ayant un profil de dopage- doped silicon substrate, having a doping profile-
défini par une implantation d'ions appartenant à un premier type d'ions donnant un dopage du même type defined by an implantation of ions belonging to a first type of ion giving doping of the same type
que celui du substrat, une source et un drain défi- than that of the substrate, a source and a defi-
nis, dans ledit substrat, par une implantation d'ions nis, in said substrate, by an implantation of ions
appartenant à un deuxième type d'ions donnant un do- belonging to a second type of ion giving a
page différent de celui du substrat, et une grille, caractérisé en ce que l'on réalise, sous la source et le drain du transistor une ou plusieurs implantations page different from that of the substrate, and a grid, characterized in that one or more implantations are made under the source and the drain of the transistor
d'ions appartenant au deuxième type d'ions, à des do- of ions belonging to the second type of ions, to do-
ses et des énergies telles qu'elles compensent le do- its and energies as it compensates for the do-
page du substrat sans en inverser le type, la grille du transistor servant de masque à cette implantation, page of the substrate without inverting the type, the gate of the transistor serving as a mask for this implantation,
et en ce que l'on soumet le substrat à un recuit. and in that the substrate is subjected to annealing.
Le fait d'utiliser la grille du transistor comme masque à l'implantation d'ions sous la source Using the transistor gate as a mask for implanting ions under the source
et le drain du transistor permet d'obtenir des ré- and the drain of the transistor makes it possible to obtain
gions de compensation auto-alignées par rapport à la compensation regions self-aligned with respect to the
grille du transistor.transistor gate.
Selon un mode préféré de mise en oeuvre du procédé selon l'invention, on soumet le substrat à un recuit transitoire, ce recuit étant effectué soit au moyen d'un faisceau laser, soit au moyen d'un faisceau d'électrons, soit encore au moyen d'un According to a preferred embodiment of the method according to the invention, the substrate is subjected to a transient annealing, this annealing being carried out either by means of a laser beam, or by means of an electron beam, or else by means of a
chauffage radiatif par lampes ou résistances chauf- radiative heating by lamps or heating resistors
fantes. L'utilisation d'un recuit transitoire par rapport à l'utilisation d'un recuit classique au four permet d'éviter la diffusion des ions implantés fantes. The use of a transient annealing compared to the use of a conventional annealing in an oven makes it possible to avoid the diffusion of the implanted ions
sous la source et le drain de transistor Ceci per- under the source and the drain of transistor This per-
met donc d'obtenir une compensation du dopage beau- therefore puts to obtain compensation for doping much
coup plus précise.more precise shot.
Selon l'invention, le substrat étant réa- According to the invention, the substrate being reacted
lisé en silicium de type P, les ions appartenant au read in type P silicon, the ions belonging to the
premier type d'ions sont des ions de bore et les- first type of ions are boron ions and the-
ions appartenant au deuxième type d'ions sont des ions belonging to the second type of ions are
ions de phosphore ou d'arsenic.phosphorus or arsenic ions.
De même, selon l'invention, le substrat- Similarly, according to the invention, the substrate-
étant réalisé en silicium de type N, les ions appar- being made of type N silicon, the ions appear
tenant au premier type d'ions sont des ions de phos- holding on to the first type of ions are phos- ions
phore ou d'arsenic et les ions appartenant au phore or arsenic and the ions belonging to
deuxième type d'ions sont des ions de bore. second type of ions are boron ions.
D'autres caractéristiques et avantages de Other features and benefits of
l'invention ressortiront mieux de la description qui the invention will emerge more clearly from the description which
va suivre, donnée à titre explicatif mais nullement limitatif, en référence aux figures annexées, sur lesquelles: la figure 1 représente, schématiquement, en coupe transversale, la structure d'un transistor MOS, will follow, given by way of explanation but in no way limiting, with reference to the appended figures, in which: FIG. 1 shows, diagrammatically, in cross section, the structure of a MOS transistor,
dans lequel on a optimisé le dopage selon l'inven- in which the doping according to the invention has been optimized
tion, et la figure 2 représente des courbes donnant la quantité d'ions implantés, exprimée en ions par tion, and figure 2 represents curves giving the quantity of implanted ions, expressed in ions by
cm 3, pour les différents dopages du substrat, ef- cm 3, for the different dopings of the substrate, ef-
fectués lors de la fabrication d'un transistor MOS à canal N, en fonction de la profondeur (P) de pénétration des ions dans le substrat exprimée en performed during the manufacture of an N-channel MOS transistor, as a function of the depth (P) of penetration of the ions into the substrate expressed in
micron, ces courbes illustrant la compensation se- micron, these curves illustrating the compensation
lon l'invention du dopage du substrat sous le ca- according to the invention of doping of the substrate under the
nal du transistor.nal of the transistor.
Afin de simplifier la description qui va In order to simplify the description which goes
suivre, on se place dans le cas d'un transistor MOS à canal N, réalisé sur un substrat de type P Bien follow, we place ourselves in the case of an N-channel MOS transistor, produced on a P-type substrate.
entendu, ce procédé est applicable au cas d'un tran- understood, this process is applicable in the case of a tran-
sistor à canal P sur un substrat de type N, les P-channel sistor on an N-type substrate, the
implantations d'ions de bore étant dans ce cas rem- boron ion implantations being in this case replaced
placées par des implantations d'ions de phosphore ou placed by implantations of phosphorus ions or
d'arsenic et inversement.arsenic and vice versa.
Sur la figure 1, on a représenté, en coupe transversale, la structure d'un transistor MOS Ce transistor MOS, réalisé sur un substrat semiconduc teur dopé 2, dans une ouverture de l'oxyde de champ In FIG. 1, the structure of a MOS transistor is shown in cross section. This MOS transistor, produced on a doped semiconductor substrate 2, in an opening of the field oxide
3, comprend, de façon classique, deux régions laté- 3, conventionally comprises two lateral regions
rales 4 et 6, correspondant respectivement -à la source et au drain de ce transistor, et une couche d'oxyde 8, recouvrant la région centrale du substrat 2, surmontée d'une couche conductrice 10 La couche conductrice 10 correspond à la grille du transistor rales 4 and 6, corresponding respectively to the source and the drain of this transistor, and an oxide layer 8, covering the central region of the substrate 2, surmounted by a conductive layer 10 The conductive layer 10 corresponds to the gate of the transistor
et la couche d'oxyde 8 à l'oxyde de grille L'ensem- and the oxide layer 8 to the gate oxide The whole
ble du transistor MOS est recouvert d'une couche d'oxyde 12, gravée de façon à définir les trous de contacts électriques du transistor, cette couche d'oxyde 12 étant elle-même recouverte d'une couche ble of the MOS transistor is covered with an oxide layer 12, etched so as to define the electrical contact holes of the transistor, this oxide layer 12 itself being covered with a layer
conductrice 14, gravée de façon à définir les con- conductor 14, engraved so as to define the con-
nexions électriques.electrical connections.
De façon classique, la fabrication de ce transistor MOS se fait, tout d'abord, en réalisant l'oxyde de champ 3 et l'oxyde de grille 8, puis en implantant des ions de bore permettant de définir le Conventionally, the manufacturing of this MOS transistor is done, first of all, by producing the field oxide 3 and the gate oxide 8, then by implanting boron ions making it possible to define the
dopage sous le canal du transistor Cette implanta- doping under the transistor channel This implanta-
tion-d'ions est par exemple effectuée à une dose de 101 atomes/cm 2 et à une énergie de 50 Ke V, puis à il 2 une dose de 4 10 atomes/cm et à une énergie de ke V. Après ce dopage du substrat 2, on réalise la grille 10 du transistor, généralement dans une couche de silicium polycristallin dopé, puis la source 4 et le drain 6 de ce transistor La source ion-ion is for example carried out at a dose of 101 atoms / cm 2 and at an energy of 50 Ke V, then at it 2 a dose of 4 10 atoms / cm and at an energy of ke V. After this doping of the substrate 2, the gate 10 of the transistor is produced, generally in a layer of doped polycrystalline silicon, then the source 4 and the drain 6 of this transistor The source
et le drain de ce transistor sont obtenus en implan- and the drain of this transistor are obtained by implanting
tant des ions de phosphore ou d'arsenic, cette im- both phosphorus or arsenic ions, this im-
plantation étant réalisée en utilisant la grille du transistor comme masque à ladite implantation Cette implantation est par exemple réalisée pour des ions d'arsenic à une dose de 5 1015 atomes/cm 2 et à une énergie de 100 ke V. planting being carried out using the transistor gate as a mask at said implantation This implantation is for example carried out for arsenic ions at a dose of 5 1015 atoms / cm 2 and at an energy of 100 ke V.
Ensuite, on dépose sur l'ensemble du subs- Then, we deposit on the entire subs-
trat 2, la couche d'oxyde 12 que l'on grave de façon à réaliser les trous de contacts électriques du transistor, puis l'on recouvre cette couche d'oxyde trat 2, the oxide layer 12 which is etched so as to produce the electrical contact holes of the transistor, then this oxide layer is covered
12 d'une couche conductrice 14, généralement en alu- 12 of a conductive layer 14, generally of aluminum
minium, que l'on grave de façon appropriée pour minium, which is engraved appropriately for
réaliser les connexions électriques du transistor. make the electrical connections of the transistor.
Selon l'invention, afin de compenser le dopage du substrat sous le canal du transistor MOS, on réalise, sous la source 4 et sous le drain 6 du transistor, une ou plusieurs implantations d'ions de phosphore ou d'arsenic suivi éventuellement d'une implantation de bore, le nombre d'implantations étant fonction de la quantité et du profil d'ions de bore servant à la définition du dopage sous le canal ainsi que du profil de ce dopage Cette implantation qui est effectuée avant de déposer la couche d'oxyde According to the invention, in order to compensate for the doping of the substrate under the channel of the MOS transistor, one or more implantations of phosphorus or arsenic ions are carried out, under the source 4 and under the drain 6 of the transistor, optionally followed by a boron implantation, the number of implantations being a function of the quantity and of the profile of boron ions used for the definition of the doping under the channel as well as of the profile of this doping This implantation which is carried out before depositing the layer oxide
12 sur le substrat permet d'obtenir deux régions la- 12 on the substrate makes it possible to obtain two regions
térales 16 et 18 situées respectivement sous la 16 and 18 located respectively under the
source 4 et sous le drain 6 du transistor. source 4 and under the drain 6 of the transistor.
Dans le cas d'une double implantation de bore définissant le dopage sous le canal, prise en In the case of a double implantation of boron defining the doping under the channel, taken into account
exemple précédemment, on pourra effectuer, pour com- example above, we can perform, for
penser ce dopage, une implantation de phosphore avec une dose de 1012 atomes/cm 2 à une énergie de think of this doping, an implantation of phosphorus with a dose of 1012 atoms / cm 2 at an energy of
ke V, suivie d'une deuxième implantation de phos- ke V, followed by a second implantation of phos-
phore à une dose de 4 101 l atomes/cm 2 à une énergie de 280 ke V, puis d'une implantation de bore avec une dose de 3 101 l atomes/cm 2 à une énergie de 80 ke V. Afin d'obtenir les deux régiuns 16 et 18 phore at a dose of 4,101 l atoms / cm 2 at an energy of 280 ke V, then of an implantation of boron with a dose of 3,101 l atoms / cm 2 at an energy of 80 ke V. In order to obtain the two regiuns 16 and 18
auto-alignées par rapport à la grille 10 du transis- self-aligned with respect to grid 10 of the transist
tor, cette implantation sera effectuée en utilisant- tor, this implantation will be carried out using-
la grille du transistor comme masque à ladite im- the transistor gate as a mask at said im-
plantation On conservera la résine ayant servi à la définition de la grille du transistor, lors de ces implantations, pour améliorer l'effet de masquage de la grille Après élimination de la résine, et afin de réarranger le réseau cristallin perturbé lors de cette implantation, on soumet le substrat 2 à un planting We will keep the resin used to define the gate of the transistor, during these implantations, to improve the masking effect of the gate After elimination of the resin, and in order to rearrange the crystal lattice disturbed during this implantation, the substrate 2 is subjected to a
recuit De préférence, on utilise un recuit transi- annealing Preferably, a transi-
toire permettant d'éviter ou de minimiser la diffu- roof to avoid or minimize diffusion
sion des ions implantés sous la source et le drain du transistor Ce recuit peut être réalisé soit au ion ions implanted under the source and the drain of the transistor This annealing can be carried out either at
moyen d'un faisceau laser, soit au moyen d'un fais- by means of a laser beam, either by means of a
ceau d'électrons, ou au moyen d'un chauffage radia- electron beam, or by radiant heating
tif par lampes ou résistances chauffantes. tif by lamps or heating resistors.
A titre d'exemple, on a représenté sur la By way of example, there is shown on the
figure 2, des courbes donnant la quantité d'ions im- figure 2, curves giving the quantity of im ions
plantés par cm 3, pour les différents dopages, effec- planted per cm 3, for the different dopings, effective
tués lors de la fabrication du transistor MOS, en fonction de la profondeur P de pénétration des ions dans le substrat Ces courbes, ou profils de dopage, sont donnés dans le cas d'un substrat en silicium de type P, c'est-à-dire dans le cas d'un transistor MOS à canal N. killed during the manufacture of the MOS transistor, as a function of the depth P of penetration of ions into the substrate These curves, or doping profiles, are given in the case of a P-type silicon substrate, that is to say - say in the case of an N-channel MOS transistor.
Le profil de dopage a correspond à l'im- The doping profile a corresponds to the im-
plantation définissant le canal du transistor, cette implantation étant faite, dans le présent exemple, plantation defining the transistor channel, this implantation being made, in the present example,
avec des ions de bore Le profil de dopage b corres- with boron ions The doping profile b corresponds to
pond à l'implantation permettant de compenser la lay in the implantation to compensate for the
précédente implantation, conformément à l'inven- previous implantation, in accordance with the invention
tion Cette implantation est réalisée, dans le pré- This implementation is carried out, in the pre-
sent exemple, avec des ions de phosphore Le profil de dopage c correspond à la résultante de la courbe sent example, with phosphorus ions The doping profile c corresponds to the result of the curve
a et de la courbe b, c'est-à-dire au profil du dopa- a and curve b, that is to say the profile of the dopa-
ge résultant des deux précédentes implantations. age resulting from the two previous settlements.
Enfin, le profil de dopage d correspond à l'implan- Finally, the doping profile d corresponds to the implant-
tation définissant la source et le drain du transis- tation defining the source and the drain of the transist
tor, cette implantation étant réalisée dans le pré- tor, this implantation being carried out in the pre-
sent exemple avec des ions de phosphore. feels example with phosphorus ions.
Le procédé de dopage, selon l'invention, de mise en oeuvre facile, permet de diminuer les capacités parasites entre la source, le drain et le The doping method, according to the invention, of easy implementation, makes it possible to reduce the stray capacitances between the source, the drain and the
substrat du transistor.transistor substrate.
Claims (6)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8211571A FR2529715A1 (en) | 1982-07-01 | 1982-07-01 | METHOD FOR OPTIMIZING DOPING IN A MOS TRANSISTOR |
| EP83401331A EP0099787A1 (en) | 1982-07-01 | 1983-06-28 | Process for optimizing the doping of a MOS transistor |
| JP58118387A JPS5921068A (en) | 1982-07-01 | 1983-07-01 | Method of optimizing doping in mos transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8211571A FR2529715A1 (en) | 1982-07-01 | 1982-07-01 | METHOD FOR OPTIMIZING DOPING IN A MOS TRANSISTOR |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2529715A1 true FR2529715A1 (en) | 1984-01-06 |
| FR2529715B1 FR2529715B1 (en) | 1984-12-21 |
Family
ID=9275586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR8211571A Granted FR2529715A1 (en) | 1982-07-01 | 1982-07-01 | METHOD FOR OPTIMIZING DOPING IN A MOS TRANSISTOR |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0099787A1 (en) |
| JP (1) | JPS5921068A (en) |
| FR (1) | FR2529715A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0255882A3 (en) * | 1986-08-07 | 1990-05-30 | Siemens Aktiengesellschaft | Npn bipolar transistor with extremely thin emitter/base structure and method for manufacturing the same |
| US4889819A (en) * | 1988-05-20 | 1989-12-26 | International Business Machines Corporation | Method for fabricating shallow junctions by preamorphizing with dopant of same conductivity as substrate |
| JPH02122568A (en) * | 1988-09-15 | 1990-05-10 | Advanced Micro Devices Inc | Metallic oxide semiconductor element having junction arranged on either side of gate and doped in high concentration relatively |
| EP0463067B1 (en) * | 1989-03-02 | 1996-06-05 | Thunderbird Technologies, Inc. | Fermi threshold field effect transistor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2337428A1 (en) * | 1975-12-31 | 1977-07-29 | Ibm | COMPOSITE CHANNEL FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING |
-
1982
- 1982-07-01 FR FR8211571A patent/FR2529715A1/en active Granted
-
1983
- 1983-06-28 EP EP83401331A patent/EP0099787A1/en not_active Withdrawn
- 1983-07-01 JP JP58118387A patent/JPS5921068A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2337428A1 (en) * | 1975-12-31 | 1977-07-29 | Ibm | COMPOSITE CHANNEL FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING |
Non-Patent Citations (4)
| Title |
|---|
| APPLIED PHYSICS LETTERS, volume 35, no. 8, octobre 1979 (NEW YORK, US) M. KOYANAGI et al. "Short-channel MOS FET's fabricated by self-aligned ion implantation and laser-annealing", pages 621-623 * |
| IBM TECHNICAL DISCLOSURE BULLETIN, volume 17, no. 4, septembre 1974 (NEW YORK; US) D.R. YOUNG "Metal-oxide semiconductor field-effect transistor structure", pages 1208-1209 * |
| IEEE ELECTRON DEVICES, volume ED-27, no. 8, août 1980 (NEW YORK, US) R.F. MOTTA et al. "Computer-aided device optimization for MOS/VLSI", pages 1559-1565 * |
| IEEE JOURNAL OF SOLID-STATE CIRCUITS, volume SC-14, no. 3, juin 1979 (NEW YORK; US) J. PEREIRA DE SOUZA et al. "A simplified self-aligned al-gate MOS technology for high performance depletion-logic circuits", pages 651-653 * |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2529715B1 (en) | 1984-12-21 |
| JPS5921068A (en) | 1984-02-02 |
| EP0099787A1 (en) | 1984-02-01 |
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