EP0158670A1 - Semiconductor integrated circuits containing complementary metal oxide semiconductor devices - Google Patents

Semiconductor integrated circuits containing complementary metal oxide semiconductor devices

Info

Publication number
EP0158670A1
EP0158670A1 EP84903741A EP84903741A EP0158670A1 EP 0158670 A1 EP0158670 A1 EP 0158670A1 EP 84903741 A EP84903741 A EP 84903741A EP 84903741 A EP84903741 A EP 84903741A EP 0158670 A1 EP0158670 A1 EP 0158670A1
Authority
EP
European Patent Office
Prior art keywords
trench
region
substrate
regions
degrees
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP84903741A
Other languages
German (de)
French (fr)
Inventor
Gerald Allan Coquin
William Thomas Lynch
Louis Carl Parrillo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=27066485&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=EP0158670(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by American Telephone and Telegraph Co Inc, AT&T Corp filed Critical American Telephone and Telegraph Co Inc
Publication of EP0158670A1 publication Critical patent/EP0158670A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

Definitions

  • the invention pertains generally to semiconductor devices and, particularly, to integrated circuits containing complementary metal oxide semiconductor devices.
  • CMOS 10 integrated circuit devices include both n- and p-channel field effect transistors (FETs) on the same substrate. While, as known, it is generally desirable to space the different transistors as closely together as possible on the substrate, a limitation in the past is that if adjacent
  • FIG. 1 is a cross-sectional view of a first embodiment of the inventive CMOS device.
  • FIGS. 2-3 are cross-sectional views of second and third embodiments of the inventive CMOS device.
  • the invention is described in connection with an integrated circuit comprising a plurality of field-effect transistors disposed within a substrate of silicon.
  • the trench filler material perferably comprises polycrystalline or amorphous silicon ("polysilicon” hereinafter) because such material can be readily deposited to completely fill a trench of proper design and because its coefficient of thermal expansion is the same as that of the silicon substrate. Both these conditions—complete, void-free filling and matching coefficient of expansion—are essential to avoid the prior art problem of excessive cracking of the trench-containing substrates.
  • silicon dioxide While it is known in the past to fill trenches with polysilicon, silicon dioxide is also used, and no distinction has been made, as far as we know, between the two materials with respect to the cracking problem. Silicon dioxide, we have discovered, however, is not a suitable filler material with silicon substrates owing to the great disparity in the coefficients of thermal expansion of these materials.
  • substrate-filler material combinations can be used. For example, it is possible to fill trenches in
  • MPI substrates of gallium arsenide with poly/crystalline gallium arsenide deposited in known manner MPI substrates of gallium arsenide with poly/crystalline gallium arsenide deposited in known manner.
  • filler materials can be used with non-identical substrate materials provided the coefficients of thermal expansion of the materials match within a factor of about 3.
  • polysilicon is a good candidate for use as a filler material in substrates of gallium arsenide and similar III-IV compounds.
  • a first embodiment of the inventive device depicted in FIG. 1, includes a substrate 20, of silicon, having a bulk region 30 of, for example, p-type conductivity (n-type conductivity is also useful) provided by a doping level ranging from about 10 15cm-3 to about 10 17cm-3. Doping levels less than about 10 15cm-3 are undesirable because they require undesirably deep trenches to significantly reduce the possibility of latchup.
  • the substrate 20 also includes a tub 40 of / conductivity type opposite to that of the bulk region 30, e.g., n-type conductivity, extending from the surface 50.
  • the depth of the tub 40 is preferably greater than about 1/2 m, while the vertical integrated doping level of the tub 40, i.e., the integral of the doping level of the tub 40 over the depth of the tub 40, ranges from about
  • the device includes a trench 140 which prevents, or substantially reduces the possibility of, latchup.
  • the trench is formed in the silicon substrate 20, and separates
  • the one or more p-channel FETs formed in the tub 40 from the one or more n-channel FETs fabricated in the bulk region 30, i.e., the trench encircles the FETs in the tub 40.
  • the trench 140 is formed after the fabrication of the tub 40 but before the fabrication of the FETs, and is preferably positioned at the juncture of the tub 40 and bulk region 30.
  • a preferred filler material 160 is polysilicon which is readily deposited into the trench 140 using, for example, known conventional chemical vapor deposition (CVD) techniques.
  • CVD chemical vapor deposition
  • two conditions are preferably met. The first is that the angle (denoted ⁇ in FIG. 1) between the trench sidewall 150 and a perpendicular to the substrate surface 50 is between about 5 to 10 degrees. It is found that trenches having steeper (e.g., vertical) walls or, worse, negative angle walls (e.g., trenches which widen towards the bottom) are quite difficult to completely fill.
  • the diverging trench walls avoid any masking effects, by the walls, of the filler material during the deposition process. Conversely, trenches having wall angles in excess of 10 degrees become too wide, thus defeating the object of small transitor spacings.
  • the second condition is that the thickness of the polysilicon deposited in the trench filling process is adequate to at least completely fill the trench. To ensure this result, a thickness which is slightly excessive is used, and the excessive material overlying the trench is slightly etched back using known processes. To prevent conduction of leakage currents, and diffusion of dopant, from the substrate 20 into the polysilicon 160, the trench 140 preferably includes a
  • OMPI relatively thin layer of a dielectric material (material whose bandgap is greater than about 2 eV) 170 covering the interior surfaces of the trench.
  • dielectric materials include Si ⁇ 2 and Si 3 N4 deposited in known fashion.
  • the thickness of the dielectric layer 170 ranges from about 200 Angstroms (A) to about 5000 A. A thickness less than about 200 A is undesirable as being ineffective to prevent short circuits through the polysilicon. A thickness greater than about 5000 A is undesirable as resulting in the formation of cracks and dislocations at the coating 170-trench wall 150 interface during high temperature processing.
  • a second embodiment of the inventive device differs from the first embodiment in that the substrate 20 includes a relatively heavily doped bulk region 32 of, for example, p-type conductivity, supporting a moderately doped, relatively thin (compared to the bulk region 32) layer 34 whose conductivity type is the same as that of the region 32.
  • the layer 34 is preferably epitaxially grown on the bulk region 32 using, for example, conventional vapor phase epitaxy.
  • a tub 40 of, for example, n-type conductivity, is formed in the moderately doped layer 34 and a trench 140 extends through the thickness of the layer 34 at least to the heavily doped bulk region 32.
  • the advantage of this arrangement is that the depth of the trench 140 is reduced (as compared to the trench employed in the first embodiment) because the heavy doping within the bulk region 32 reduces the lifetime of minority charge carriers therethrough which would otherwise cause latchup between the two MOS devices shown.
  • the doping level within the bulk region 32 ranges from about 10 17 to about 1021cm-3, and is preferably about 10 20cm-3.
  • a doping level less than about 10 17cm—3 is undesirable because so low a doping level does not significantly reduce the possibility of latchup.
  • a doping level greater than about 10 21cm—3 is undesirable because so high a doping level results in an undesirably large out-diffusion of dopant from the bulk region 32 into the layer 34.
  • the layer 34 has a thickness ranging from about
  • the tub 40 has a thickness greater than about
  • a third embodiment of the inventive device is generally similar to the second embodiment except that the depth of the trench 140 is reduced by the depth of a relatively heavily doped region 190 within the layer 34, extending from the bottom of " the trench into the bulk region 32.
  • the conductivity type and the doping level range for the region 190 is the same as that for the bulk region 32, and thus the region 190 is essentially an extension of the bulk ⁇ region 32 into the layer 34.
  • the region 190 serves the same purpose as the bulk region 32, i.e., it reduces the lifetime of minority carriers therethrough (while decreasing trench depth) .
  • the region 190 is formed by implanting donor or acceptor ions (depending on whether the region 190 is to be of ni or p + -type conductivity) into the semiconductor material adjacent the bottom of the trench, and then diffusing these ions toward the bulk region 32 with a heat treatment. Because ions diffuse both vertically and laterally, vertical diffusion, and thus the depth of region 190, is preferably less than about 4 ⁇ m to avoid
  • Ion implantation preferably occurs after the formation of the dielectric layer 170 on the walls of the trench 140 (and before the deposition of the polysilicon). Because the trench sidewall 150 is inclined to the vertical (as viewed in FIG. 4), and because the ions travel an essentially vertical path, the ions impinging the sidewall of the trench must penetrate a greater thickness of dielectric material than the ions impinging the bottom of the trench to reach the underlying semiconductor material. Thus, relatively few, if any, ions penetrate the sidewall 150 into the tub 40.
  • acceptor ions such as boron ions
  • useful dopant implantation levels range from

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

Un dispositif à circuit intégré CMOS, permettant d'éviter les blocages entre des FETs à canal n et à canal p faiblement écartés (90, 130) du dispositif, comprend une tranchée (150) empêchant les blocages, formée dans le substrat semi-conducteur (20) entre les FETs. La tranchée est pratiquement entièrement remplie d'un matériau diélectrique solide (160) essentiellement exempt de cavités provoquant des fissures, et elle est étroite, étant donné que l'angle entre la paroi latérale de la tranchée et une perpendiculaire à la surface du substrat (50) est supérieur ou égal à 5 degrés environ mais inférieur à 10 degrés environ.A CMOS integrated circuit device, making it possible to avoid blockages between n-channel and p-channel FETs slightly spaced apart (90, 130) from the device, comprises a trench (150) preventing blockages, formed in the semiconductor substrate (20) between FETs. The trench is almost entirely filled with a solid dielectric material (160) essentially free of cracks causing cracks, and it is narrow, since the angle between the side wall of the trench and a perpendicular to the surface of the substrate ( 50) is greater than or equal to about 5 degrees but less than about 10 degrees.

Description

SEMICONDUCTOR INTEGRATED CIRCUITS CONTAINING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICES
Background of the Invention 5 The invention pertains generally to semiconductor devices and, particularly, to integrated circuits containing complementary metal oxide semiconductor devices.
Complementary metal oxide semiconductor (CMOS) 10 integrated circuit devices include both n- and p-channel field effect transistors (FETs) on the same substrate. While, as known, it is generally desirable to space the different transistors as closely together as possible on the substrate, a limitation in the past is that if adjacent
15 different type transistors (e.g., p and n channel field effect transistors) are too close together they can _■*?- improperly electrically interact or "latchup" owing to the flow of leakage currents therebetween. One known solution is the use of dielectric material filled trenches extending
2.0 into the substrate between adjacent transistors. One problem, however, is that semiconductor substrates containing such trenches have, in the past, been excessively susceptible to cracking. Also, to obtain adequate isolation between the adjacent transistors, 5 relatively deep trenches have been required. The deeper the trenches, however, the longer and more costly the fabrication process and the more likely are the substrates to crack. Summary of the Invention 0 We have discovered, as part of our invention, that a major cause of the cracking of prior art trench- containing substrates is that the trenches are often not completely filled with the dielectric material, voids being present therewithin. Based upon this discovery, the 5 trenches used in our inventive devices are completely filled with the dielectric material, and, to facilitate obtaining such complete filling, the trench walls diverge slightly in the upward direction, but not in excess of 10 degrees from the vertical.
In a further embodiment of the invention, the trenches extend into or to a region of heavily doped semiconductor material providing a barrier to leakage currents between the trench-separated transistors. The presence of such leakage barrier reduces the depth of the trenches otherwise necessary. Brief Description of the Drawing FIG. 1 is a cross-sectional view of a first embodiment of the inventive CMOS device; and
FIGS. 2-3 are cross-sectional views of second and third embodiments of the inventive CMOS device. Detailed Description The invention is described in connection with an integrated circuit comprising a plurality of field-effect transistors disposed within a substrate of silicon. With a silicon substrate, the trench filler material perferably comprises polycrystalline or amorphous silicon ("polysilicon" hereinafter) because such material can be readily deposited to completely fill a trench of proper design and because its coefficient of thermal expansion is the same as that of the silicon substrate. Both these conditions—complete, void-free filling and matching coefficient of expansion—are essential to avoid the prior art problem of excessive cracking of the trench-containing substrates.
While it is known in the past to fill trenches with polysilicon, silicon dioxide is also used, and no distinction has been made, as far as we know, between the two materials with respect to the cracking problem. Silicon dioxide, we have discovered, however, is not a suitable filler material with silicon substrates owing to the great disparity in the coefficients of thermal expansion of these materials.
Other substrate-filler material combinations can be used. For example, it is possible to fill trenches in
MPI substrates of gallium arsenide with poly/crystalline gallium arsenide deposited in known manner.
In general, provided the filler material adequately adheres to the trench walls, filler materials can be used with non-identical substrate materials provided the coefficients of thermal expansion of the materials match within a factor of about 3.
Thus, for example, because of its ease of deposition, and because of an adequate matching of coefficients of thermal expansion, polysilicon is a good candidate for use as a filler material in substrates of gallium arsenide and similar III-IV compounds.
A first embodiment of the inventive device, depicted in FIG. 1, includes a substrate 20, of silicon, having a bulk region 30 of, for example, p-type conductivity (n-type conductivity is also useful) provided by a doping level ranging from about 10 15cm-3 to about 10 17cm-3. Doping levels less than about 10 15cm-3 are undesirable because they require undesirably deep trenches to significantly reduce the possibility of latchup.
The substrate 20 also includes a tub 40 of / conductivity type opposite to that of the bulk region 30, e.g., n-type conductivity, extending from the surface 50. The depth of the tub 40 is preferably greater than about 1/2 m, while the vertical integrated doping level of the tub 40, i.e., the integral of the doping level of the tub 40 over the depth of the tub 40, ranges from about
12 I c • ___
10 to about 10 cm , and is preferably 13 _2 about 10 cm . A depth less than about 1/2 ym, and/or a vertical integrated doping level less than about 10 12cm-2, often result in undesirable punchthrough from the source (of an FET formed in the tub 40) to the bulk region 30. The device includes a trench 140 which prevents, or substantially reduces the possibility of, latchup. The trench is formed in the silicon substrate 20, and separates
P the one or more p-channel FETs formed in the tub 40 from the one or more n-channel FETs fabricated in the bulk region 30, i.e., the trench encircles the FETs in the tub 40. Preferably, the trench 140 is formed after the fabrication of the tub 40 but before the fabrication of the FETs, and is preferably positioned at the juncture of the tub 40 and bulk region 30.
As previously noted, it is essential to completely fill the trench to avoid cracks which can develop during subsequent high temperature processing. A preferred filler material 160 is polysilicon which is readily deposited into the trench 140 using, for example, known conventional chemical vapor deposition (CVD) techniques. In accordance with this invention, to avoid cracks and/or voids in the polysilicon, two conditions are preferably met. The first is that the angle (denoted α in FIG. 1) between the trench sidewall 150 and a perpendicular to the substrate surface 50 is between about 5 to 10 degrees. It is found that trenches having steeper (e.g., vertical) walls or, worse, negative angle walls (e.g., trenches which widen towards the bottom) are quite difficult to completely fill. The diverging trench walls avoid any masking effects, by the walls, of the filler material during the deposition process. Conversely, trenches having wall angles in excess of 10 degrees become too wide, thus defeating the object of small transitor spacings.
The second condition is that the thickness of the polysilicon deposited in the trench filling process is adequate to at least completely fill the trench. To ensure this result, a thickness which is slightly excessive is used, and the excessive material overlying the trench is slightly etched back using known processes. To prevent conduction of leakage currents, and diffusion of dopant, from the substrate 20 into the polysilicon 160, the trench 140 preferably includes a
OMPI relatively thin layer of a dielectric material (material whose bandgap is greater than about 2 eV) 170 covering the interior surfaces of the trench. Useful dielectric materials include Siθ2 and Si3N4 deposited in known fashion. The thickness of the dielectric layer 170 (if employed) ranges from about 200 Angstroms (A) to about 5000 A. A thickness less than about 200 A is undesirable as being ineffective to prevent short circuits through the polysilicon. A thickness greater than about 5000 A is undesirable as resulting in the formation of cracks and dislocations at the coating 170-trench wall 150 interface during high temperature processing.
Techniques for forming the trenches, e.g., by known masking and etching procedures, can be used. Preferrably, the etching of the substrate to form the trenches is done by a known reactive-ion-etching process. As generally known, by controlling the etch rate of the process, the angle of slope of the trench walls can be selected. With reference to FIG. 2, a second embodiment of the inventive device differs from the first embodiment in that the substrate 20 includes a relatively heavily doped bulk region 32 of, for example, p-type conductivity, supporting a moderately doped, relatively thin (compared to the bulk region 32) layer 34 whose conductivity type is the same as that of the region 32. The layer 34 is preferably epitaxially grown on the bulk region 32 using, for example, conventional vapor phase epitaxy. A tub 40 of, for example, n-type conductivity, is formed in the moderately doped layer 34 and a trench 140 extends through the thickness of the layer 34 at least to the heavily doped bulk region 32. The advantage of this arrangement is that the depth of the trench 140 is reduced (as compared to the trench employed in the first embodiment) because the heavy doping within the bulk region 32 reduces the lifetime of minority charge carriers therethrough which would otherwise cause latchup between the two MOS devices shown. The doping level within the bulk region 32 ranges from about 10 17 to about 1021cm-3, and is preferably about 10 20cm-3. A doping level less than about 10 17cm—3 is undesirable because so low a doping level does not significantly reduce the possibility of latchup. A doping level greater than about 10 21cm—3 is undesirable because so high a doping level results in an undesirably large out-diffusion of dopant from the bulk region 32 into the layer 34. The layer 34 has a thickness ranging from about
1 μm to about 10 μm, and a doping level ranging from about
1014 to about 1017cπf3.
The tub 40 has a thickness greater than about
1/2 μm but less than the thickness of the layer 34, and a vertical integrated doping level ranging from about
12 15 —2
10 to about 10 cm .
With reference to "FIG. 3, a third embodiment of the inventive device is generally similar to the second embodiment except that the depth of the trench 140 is reduced by the depth of a relatively heavily doped region 190 within the layer 34, extending from the bottom of" the trench into the bulk region 32. The conductivity type and the doping level range for the region 190 is the same as that for the bulk region 32, and thus the region 190 is essentially an extension of the bulk ■ region 32 into the layer 34. The region 190 serves the same purpose as the bulk region 32, i.e., it reduces the lifetime of minority carriers therethrough (while decreasing trench depth) . The region 190 is formed by implanting donor or acceptor ions (depending on whether the region 190 is to be of ni or p+-type conductivity) into the semiconductor material adjacent the bottom of the trench, and then diffusing these ions toward the bulk region 32 with a heat treatment. Because ions diffuse both vertically and laterally, vertical diffusion, and thus the depth of region 190, is preferably less than about 4 μm to avoid
-^TREX
OMPI undesirable lateral diffusion of dopant into the tub 40.
Ion implantation preferably occurs after the formation of the dielectric layer 170 on the walls of the trench 140 (and before the deposition of the polysilicon). Because the trench sidewall 150 is inclined to the vertical (as viewed in FIG. 4), and because the ions travel an essentially vertical path, the ions impinging the sidewall of the trench must penetrate a greater thickness of dielectric material than the ions impinging the bottom of the trench to reach the underlying semiconductor material. Thus, relatively few, if any, ions penetrate the sidewall 150 into the tub 40.
If, for example, acceptor ions, such as boron ions, are used to dope the region 190, then useful dopant implantation levels (dopant per unit area) range from
Λ Λ *1 *7 about 10 to about 10 cm" . An implantation level less than about 10 14cm-2 i.s undesirable because this results in an undesirably low dopant concentration (dopant per unit volume) in the region 190. An implantation level greater than about 10 17cm-2 i.s undesi.rable because so great an implantation level is more than is required to achieve the desired dopant concentration, and requires an undesirably long time to achieve.

Claims

Claims
1. A semiconductor integrated device comprising: a semiconductor substrate (20) which includes first (30) and second (40) regions extending from a surface 5 (50) of said substrate, the conductivity type of the second region being opposite to that of the first region; said first and second regions including, respectively, first (130) and second (90) field effect transistors, the channel conductivity type of said first
10 transistor and of said second transistor being opposite, respectively, to the conductivity type of said first region and of said second region, and a trench (140) containing a dielectric filler material (160) extending from said surface into said substrate between said first and second
'15 regions, characterized in that the side walls of said trench diverge in a direction upwards from the trench bottom, the angle of said walls from the vertical being from about 5 degrees to about 10 degrees, and said filler material completely filling said trench and being
20 essentially free of voids.
2. The device of claim 1 wherein said semiconductor substrate is of silicon and said filler material is of polysilicon.
3. The device of claim 1 in which both said first 25 and second regions overlie a third region (FIG. 3, 32) of said substrate more heavily doped than said first and second regions and wherein, in a first embodiment (FIG. 2) said trench extends into said third region and, in a second embodiment (FIG. 3), the bottom of said trench is 30 contiguous with an extension (190) of said third region, whereby, in both said embodiments, said third region cooperates with said trench for preventing unintended latchup of said two transistors.
EP84903741A 1983-10-11 1984-10-04 Semiconductor integrated circuits containing complementary metal oxide semiconductor devices Pending EP0158670A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US54062483A 1983-10-11 1983-10-11
US54062383A 1983-10-11 1983-10-11
US540624 1983-10-11
US540623 1983-10-11

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EP0158670A1 true EP0158670A1 (en) 1985-10-23

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EP84306756A Expired EP0138517B1 (en) 1983-10-11 1984-10-04 Semiconductor integrated circuits containing complementary metal oxide semiconductor devices
EP84903741A Pending EP0158670A1 (en) 1983-10-11 1984-10-04 Semiconductor integrated circuits containing complementary metal oxide semiconductor devices

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EP (2) EP0138517B1 (en)
KR (1) KR850700087A (en)
DE (1) DE3472604D1 (en)
WO (1) WO1985001836A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656730A (en) * 1984-11-23 1987-04-14 American Telephone And Telegraph Company, At&T Bell Laboratories Method for fabricating CMOS devices
SE8603126L (en) * 1985-08-05 1987-02-06 Rca Corp CMOS INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING A SUIT
GB2183907B (en) * 1985-11-27 1989-10-04 Raytheon Co Semiconductor device
US4936928A (en) * 1985-11-27 1990-06-26 Raytheon Company Semiconductor device
US4826781A (en) * 1986-03-04 1989-05-02 Seiko Epson Corporation Semiconductor device and method of preparation
US4729006A (en) * 1986-03-17 1988-03-01 International Business Machines Corporation Sidewall spacers for CMOS circuit stress relief/isolation and method for making
US5223731A (en) * 1988-06-30 1993-06-29 Goldstar Electron Co., Ltd. EPROM cell using trench isolation to provide leak current immunity
KR970000652B1 (en) * 1988-06-30 1997-01-16 엘지반도체 주식회사 Eprom cell & method of manufacturing
EP0382865A1 (en) * 1989-02-14 1990-08-22 Siemens Aktiengesellschaft Arrangement to reduce latch-up sensitivity in CMOS semiconductor circuits
EP1195260A3 (en) 2000-10-03 2002-08-14 Fuji Photo Film Co., Ltd. Heat-sensitive recording material

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Publication number Priority date Publication date Assignee Title
EP0048175B1 (en) * 1980-09-17 1986-04-23 Hitachi, Ltd. Semiconductor device and method of manufacturing the same
US4486266A (en) * 1983-08-12 1984-12-04 Tektronix, Inc. Integrated circuit method

Non-Patent Citations (1)

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Title
See references of WO8501836A1 *

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EP0138517A1 (en) 1985-04-24
WO1985001836A1 (en) 1985-04-25
KR850700087A (en) 1985-10-21
EP0138517B1 (en) 1988-07-06
DE3472604D1 (en) 1988-08-11

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