FR2517503B1 - Substrat comportant un motif constitue d'un alliage d'or, d'un metal noble et d'un metal de base, le motif etant isole par des oxydes des metaux nobles et de base - Google Patents
Substrat comportant un motif constitue d'un alliage d'or, d'un metal noble et d'un metal de base, le motif etant isole par des oxydes des metaux nobles et de baseInfo
- Publication number
- FR2517503B1 FR2517503B1 FR8219980A FR8219980A FR2517503B1 FR 2517503 B1 FR2517503 B1 FR 2517503B1 FR 8219980 A FR8219980 A FR 8219980A FR 8219980 A FR8219980 A FR 8219980A FR 2517503 B1 FR2517503 B1 FR 2517503B1
- Authority
- FR
- France
- Prior art keywords
- noble
- pattern
- metal
- base
- oxides
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0315—Oxidising metal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1142—Conversion of conductive material into insulating material or into dissolvable compound
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12389—All metal or with adjacent metals having variation in thickness
- Y10T428/12396—Discontinuous surface component
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19051881A JPS5893297A (ja) | 1981-11-30 | 1981-11-30 | 導体回路の形成方法 |
JP8291782A JPS58199589A (ja) | 1982-05-17 | 1982-05-17 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2517503A1 FR2517503A1 (fr) | 1983-06-03 |
FR2517503B1 true FR2517503B1 (fr) | 1986-02-07 |
Family
ID=26423947
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR8219980A Expired FR2517503B1 (fr) | 1981-11-30 | 1982-11-29 | Substrat comportant un motif constitue d'un alliage d'or, d'un metal noble et d'un metal de base, le motif etant isole par des oxydes des metaux nobles et de base |
Country Status (2)
Country | Link |
---|---|
US (2) | US4628149A (fr) |
FR (1) | FR2517503B1 (fr) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4628149A (en) * | 1981-11-30 | 1986-12-09 | Nippon Electric Co., Ltd. | Substrate having a pattern of an alloy of gold and a noble and a base metal with the pattern isolated by oxides of the noble and the base metals |
DE3675321D1 (de) * | 1985-08-16 | 1990-12-06 | Dai Ichi Seiko Co Ltd | Halbleiteranordnung mit packung vom steckerstifttyp. |
CN1003524B (zh) * | 1985-10-14 | 1989-03-08 | 株式会社日立制作所 | 无电浸镀金溶液 |
US4855871A (en) * | 1987-03-05 | 1989-08-08 | Optical Materials, Inc. | Thin film semiconductor interconnect module |
JPS6418246A (en) * | 1987-07-14 | 1989-01-23 | Shinko Electric Ind Co | Lead frame for semiconductor device |
US4931144A (en) * | 1987-07-31 | 1990-06-05 | Texas Instruments Incorporated | Self-aligned nonnested sloped via |
JPH02324A (ja) * | 1987-12-18 | 1990-01-05 | Mitsui Mining & Smelting Co Ltd | 導電膜回路およびその製造方法 |
US4910643A (en) * | 1988-06-06 | 1990-03-20 | General Electric Company | Thick film, multi-layer, ceramic interconnected circuit board |
KR920005459B1 (ko) * | 1988-08-30 | 1992-07-04 | 가부시기가이샤 히다찌세이사꾸쇼 | 금속의 균질화방법 및 회로기판 |
US5183973A (en) * | 1989-08-14 | 1993-02-02 | Santa Barbara Research Center | Flexible cable for interconnecting electronic components |
JPH0383398A (ja) * | 1989-08-26 | 1991-04-09 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法 |
US5127998A (en) * | 1990-01-02 | 1992-07-07 | General Electric Company | Area-selective metallization process |
US5230965A (en) * | 1990-01-02 | 1993-07-27 | General Electric Company | High density interconnect with electroplated conductors |
JP3271272B2 (ja) * | 1991-11-12 | 2002-04-02 | 日本電気株式会社 | 半導体装置の製造方法 |
US5619018A (en) * | 1995-04-03 | 1997-04-08 | Compaq Computer Corporation | Low weight multilayer printed circuit board |
US6515233B1 (en) * | 2000-06-30 | 2003-02-04 | Daniel P. Labzentis | Method of producing flex circuit with selectively plated gold |
US6761963B2 (en) * | 2000-09-21 | 2004-07-13 | Michael D. Casper | Integrated thin film capacitor/inductor/interconnect system and method |
US6890629B2 (en) * | 2001-09-21 | 2005-05-10 | Michael D. Casper | Integrated thin film capacitor/inductor/interconnect system and method |
DE102006060408A1 (de) * | 2006-12-20 | 2008-06-26 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung korrosionsbeständiger Metalloberflächen und Reflektor mit metallischer Oberfläche |
KR101148226B1 (ko) * | 2010-05-24 | 2012-05-22 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
US9425090B2 (en) * | 2014-09-19 | 2016-08-23 | Infineon Technologies Austria Ag | Method of electrodepositing gold on a copper seed layer to form a gold metallization structure |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2780543A (en) * | 1955-05-17 | 1957-02-05 | Baker & Co Inc | High resistivity alloy |
US3386894A (en) * | 1964-09-28 | 1968-06-04 | Northern Electric Co | Formation of metallic contacts |
DE1765945A1 (de) * | 1968-08-14 | 1971-12-02 | Ibm Deutschland | Verfahren zum Herstellen einer gedruckten Schaltung mit in mehreren Ebenen verlaufenden flaechenhaften Leiterzuegen |
GB1287791A (en) * | 1968-10-31 | 1972-09-06 | Honeywell Inf Systems | A microcircuit and manufacture of same |
US3621442A (en) * | 1968-11-07 | 1971-11-16 | Allen Bradley Co | Terminal connection of electronic devices |
US3576722A (en) * | 1969-03-26 | 1971-04-27 | Bendix Corp | Method for metalizing ceramics |
US3663279A (en) * | 1969-11-19 | 1972-05-16 | Bell Telephone Labor Inc | Passivated semiconductor devices |
GB1369627A (en) * | 1970-12-18 | 1974-10-09 | Hitachi Ltd | Method for manufacturing a printed ceramic substrate |
US4014689A (en) * | 1972-05-10 | 1977-03-29 | Siemens Aktiengesellschaft | Method of fabricating a contact material for high-power vacuum circuit breakers |
US3808049A (en) * | 1972-06-02 | 1974-04-30 | Microsystems Int Ltd | Multi-layer thin-film circuits |
US4016050A (en) * | 1975-05-12 | 1977-04-05 | Bell Telephone Laboratories, Incorporated | Conduction system for thin film and hybrid integrated circuits |
US4153518A (en) * | 1977-11-18 | 1979-05-08 | Tektronix, Inc. | Method of making a metalized substrate having a thin film barrier layer |
JPS54127414A (en) * | 1978-03-27 | 1979-10-03 | Tokyo Shibaura Electric Co | Metallizing ceramic substrate |
JPS5563900A (en) * | 1978-11-08 | 1980-05-14 | Fujitsu Ltd | Multilyaer ceramic circuit board |
JPS55115392A (en) * | 1979-02-27 | 1980-09-05 | Tokyo Shibaura Electric Co | Method of fabricating hybrid circuit board |
JPS5649535A (en) * | 1979-09-28 | 1981-05-06 | Tanaka Kikinzoku Kogyo Kk | Bonding wire for semiconductor device |
FR2476913B1 (fr) * | 1980-02-25 | 1985-09-13 | Nippon Electric Co | Circuit a plusieurs couches pour integration a grande echelle et procede de fabrication de ce circuit |
EP0074605B1 (fr) * | 1981-09-11 | 1990-08-29 | Kabushiki Kaisha Toshiba | Procédé pour fabriquer un substrat pour circuit multicouches |
US4628149A (en) * | 1981-11-30 | 1986-12-09 | Nippon Electric Co., Ltd. | Substrate having a pattern of an alloy of gold and a noble and a base metal with the pattern isolated by oxides of the noble and the base metals |
-
1982
- 1982-11-24 US US06/444,097 patent/US4628149A/en not_active Expired - Fee Related
- 1982-11-29 FR FR8219980A patent/FR2517503B1/fr not_active Expired
-
1986
- 1986-12-09 US US06/940,165 patent/US4786523A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US4628149A (en) | 1986-12-09 |
FR2517503A1 (fr) | 1983-06-03 |
US4786523A (en) | 1988-11-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |