FR2444298A1 - Ensemble multiprocesseur a anti-memoire - Google Patents

Ensemble multiprocesseur a anti-memoire

Info

Publication number
FR2444298A1
FR2444298A1 FR7834929A FR7834929A FR2444298A1 FR 2444298 A1 FR2444298 A1 FR 2444298A1 FR 7834929 A FR7834929 A FR 7834929A FR 7834929 A FR7834929 A FR 7834929A FR 2444298 A1 FR2444298 A1 FR 2444298A1
Authority
FR
France
Prior art keywords
data
memory
cache memory
multiprocessor system
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7834929A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Automation Inc
Original Assignee
General Automation Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Automation Inc filed Critical General Automation Inc
Priority to FR7834929A priority Critical patent/FR2444298A1/fr
Publication of FR2444298A1 publication Critical patent/FR2444298A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)

Abstract

Appareil de multitraitement comportant une pluralité d'unités centrales 10, 12, 14 comportant chacune des moyens pour réclencher une demande d'accès à la mémoire à une adresse désignée Est en outre prévue une pluralité d'unités anti-mémoire 16, 18, 20 rapides, respectivement reliées à l'une des unités centrales et aussi à une mémoire principale 22 à accès direct. Dans chaque unité anti-mémoire, des moyens répondent à une demande de mémoire et à une adresse provenant de l'unité centrale associée, en déclenchant un cycle de mémoire dans l'unité anti-mémoire à l'adresse désignée; et des moyens déclenchent un cycle de mémoire dans la mémoire principale, par l'intermédiaire du bus commun, en réponse à une demande d'accès à la mémoire d'une unité centrale Applications informatiques.
FR7834929A 1978-12-12 1978-12-12 Ensemble multiprocesseur a anti-memoire Withdrawn FR2444298A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7834929A FR2444298A1 (fr) 1978-12-12 1978-12-12 Ensemble multiprocesseur a anti-memoire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7834929A FR2444298A1 (fr) 1978-12-12 1978-12-12 Ensemble multiprocesseur a anti-memoire

Publications (1)

Publication Number Publication Date
FR2444298A1 true FR2444298A1 (fr) 1980-07-11

Family

ID=9215978

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7834929A Withdrawn FR2444298A1 (fr) 1978-12-12 1978-12-12 Ensemble multiprocesseur a anti-memoire

Country Status (1)

Country Link
FR (1) FR2444298A1 (fr)

Similar Documents

Publication Publication Date Title
HK1019250A1 (en) Microprocessor architecture capable of supporting multiple heterogenous processors
DE3169774D1 (en) Method and device to control the conflicts posed by multiple accesses to a same cache-memory of a digital data processing system comprising at least two processors each possessing a cache
KR910001555A (ko) 데이타 프로세서
US3343140A (en) Banked memory system
EP0275157A3 (fr) Système commandé par accès direct à mémoire
ES8606696A1 (es) Sistema de ordenador digital
JPS5786959A (en) Data transfer control system
GB1264167A (fr)
JPS56123051A (en) Data transfer system in master slave system
JPH0128972B2 (fr)
FR2444298A1 (fr) Ensemble multiprocesseur a anti-memoire
JPS5466727A (en) Access control system for buffer memory
JPS54148328A (en) Buffer memory control system
JPS57141768A (en) High speed transferring device for video information
JPS5613576A (en) Memory access control system
JPS54140841A (en) Memory control system of multiprocessor system
JPS645341B2 (fr)
GB2035632A (en) Multiprocessor system
JPS5561866A (en) Memory designation system
JPS56157520A (en) Dma system without cycle steal
GB2011134A (en) Data processing system including a cache store
JPS5563422A (en) Data transfer system
JPS6363940B2 (fr)
JPS56118159A (en) Common storage device
JPH0324698B2 (fr)

Legal Events

Date Code Title Description
ST Notification of lapse