GB2011134A - Data processing system including a cache store - Google Patents

Data processing system including a cache store

Info

Publication number
GB2011134A
GB2011134A GB7845974A GB7845974A GB2011134A GB 2011134 A GB2011134 A GB 2011134A GB 7845974 A GB7845974 A GB 7845974A GB 7845974 A GB7845974 A GB 7845974A GB 2011134 A GB2011134 A GB 2011134A
Authority
GB
United Kingdom
Prior art keywords
cache store
main memory
word
data
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7845974A
Other versions
GB2011134B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/863,091 external-priority patent/US4195340A/en
Priority claimed from US05/863,093 external-priority patent/US4214303A/en
Priority claimed from US05/863,095 external-priority patent/US4157587A/en
Priority claimed from US05/863,092 external-priority patent/US4167782A/en
Priority claimed from US05/863,102 external-priority patent/US4195343A/en
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of GB2011134A publication Critical patent/GB2011134A/en
Application granted granted Critical
Publication of GB2011134B publication Critical patent/GB2011134B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02B—INTERNAL-COMBUSTION PISTON ENGINES; COMBUSTION ENGINES IN GENERAL
    • F02B75/00—Other engines
    • F02B75/02—Engines characterised by their cycles, e.g. six-stroke
    • F02B2075/022—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle
    • F02B2075/027—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle four
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6022—Using a prefetch buffer or dedicated prefetch cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)

Abstract

A data processing system includes a main memory system, a high speed buffer cache store, a central processor unit (CPU) and an Input/Output processor (IOP) all connected to a a system bus. Apparatus in the cache store reads all information on the system bus into a first in, first out buffer comprising a plurality of registers, a write address counter, a read address counter and a means for selectively processing the information. The cache store is word oriented and further comprises a directory, a data buffer and associated control logic. The CPU requests data words by sending a main memory address of the requested data word to the cache store. If the cache store does not have the requested data word apparatus in the cache store requests the data word from the main memory system, and in addition, the apparatus requests additional data words from consecutively higher addresses. If the main memory system is busy, the cache store has apparatus to request fewer words. The cache store is organized in levels. Data from a particular portion of main memory is transferred to these levels on a first in-first out basis. Apparatus in the form of round robin logic circuitry makes the first in-first out level selection. Apparatus also exists for resetting the round robin count during the initialization procedure. Apparatus in the cache store monitors each communication between system units to determine if it is a communication from a system unit to the main memory system which will update a word location in main memory. If that word location is also stored in the cache store then the word location in the cache store will be updated in addition to the word location in main memory.
GB7845974A 1977-12-22 1978-11-24 Data processing systems Expired GB2011134B (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US05/863,091 US4195340A (en) 1977-12-22 1977-12-22 First in first out activity queue for a cache store
US05/863,093 US4214303A (en) 1977-12-22 1977-12-22 Word oriented high speed buffer memory system connected to a system bus
US05/863,095 US4157587A (en) 1977-12-22 1977-12-22 High speed buffer memory system with word prefetch
US05/863,092 US4167782A (en) 1977-12-22 1977-12-22 Continuous updating of cache store
US05/863,102 US4195343A (en) 1977-12-22 1977-12-22 Round robin replacement for a cache store

Publications (2)

Publication Number Publication Date
GB2011134A true GB2011134A (en) 1979-07-04
GB2011134B GB2011134B (en) 1982-07-07

Family

ID=27542268

Family Applications (4)

Application Number Title Priority Date Filing Date
GB8029420A Expired GB2056135B (en) 1977-12-22 1978-11-24 Data processing system including a cache store
GB8029421A Expired GB2055233B (en) 1977-12-22 1978-11-24 Data processing system including a cache store
GB8029419A Expired GB2056134B (en) 1977-12-22 1978-11-24 Data processing system including a cache store
GB7845974A Expired GB2011134B (en) 1977-12-22 1978-11-24 Data processing systems

Family Applications Before (3)

Application Number Title Priority Date Filing Date
GB8029420A Expired GB2056135B (en) 1977-12-22 1978-11-24 Data processing system including a cache store
GB8029421A Expired GB2055233B (en) 1977-12-22 1978-11-24 Data processing system including a cache store
GB8029419A Expired GB2056134B (en) 1977-12-22 1978-11-24 Data processing system including a cache store

Country Status (3)

Country Link
DE (1) DE2855856A1 (en)
FR (1) FR2412910B1 (en)
GB (4) GB2056135B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0287334A2 (en) * 1987-04-13 1988-10-19 Prime Computer, Inc. High availability cache memory

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0348628A3 (en) * 1988-06-28 1991-01-02 International Business Machines Corporation Cache storage system
DE4127579A1 (en) * 1991-08-21 1993-02-25 Standard Elektrik Lorenz Ag STORAGE UNIT WITH AN ADDRESS GENERATOR
DE69334046T2 (en) * 1992-02-28 2007-02-08 Oki Electric Industry Co., Ltd. Cache memory device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1485758A (en) * 1973-09-16 1977-09-14 Hawker Siddeley Dynamics Ltd Computer systems
US3840863A (en) * 1973-10-23 1974-10-08 Ibm Dynamic storage hierarchy system
FR129151A (en) * 1974-02-09
DE2605617A1 (en) * 1976-02-12 1977-08-18 Siemens Ag CIRCUIT ARRANGEMENT FOR ADDRESSING DATA

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0287334A2 (en) * 1987-04-13 1988-10-19 Prime Computer, Inc. High availability cache memory
EP0287334A3 (en) * 1987-04-13 1989-11-08 Prime Computer, Inc. High availability cache memory

Also Published As

Publication number Publication date
GB2056135A (en) 1981-03-11
FR2412910B1 (en) 1986-04-11
GB2011134B (en) 1982-07-07
GB2056135B (en) 1982-11-24
DE2855856C2 (en) 1989-08-03
FR2412910A1 (en) 1979-07-20
GB2055233A (en) 1981-02-25
GB2055233B (en) 1982-11-24
GB2056134A (en) 1981-03-11
GB2056134B (en) 1982-10-13
DE2855856A1 (en) 1980-01-10

Similar Documents

Publication Publication Date Title
KR102319809B1 (en) A data processing system and method for handling multiple transactions
US4736293A (en) Interleaved set-associative memory
US5398325A (en) Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems
US4493026A (en) Set associative sector cache
US4912632A (en) Memory control subsystem
KR880000299B1 (en) Cash apparatus
US3761881A (en) Translation storage scheme for virtual memory system
KR920008430B1 (en) Read in process memory apparatus
EP0090575B1 (en) Memory system
CA1290073C (en) Move-out queue buffer
EP0090026B1 (en) Cache memory using a lowest priority replacement circuit
US4805098A (en) Write buffer
EP0022829B1 (en) Data processing system
US5526508A (en) Cache line replacing system for simultaneously storing data into read and write buffers having multiplexer which controls by counter value for bypassing read buffer
US7243194B2 (en) Method to preserve ordering of read and write operations in a DMA system by delaying read access
GB1387043A (en) Data processing system
KR920010442A (en) Multiprocessor system with shared memory divided into multiple banks
JPH0337744A (en) Data processor
KR960001945B1 (en) Apparatus for increasing the number of hits in a translation
GB1507284A (en) Microprogrammed data processing apparatus
KR0175983B1 (en) Data processing system having demand based write through cache with enforced ordering
JPH0721085A (en) Streaming cache for caching of data transferred between memory and i/o device and its method
US5161219A (en) Computer system with input/output cache
KR19980086620A (en) Memory controller with queue and snoop table
GB2011134A (en) Data processing system including a cache store

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee